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公开(公告)号：WO2020112239A1
公开(公告)日：2020-06-04
申请号：PCT/US2019/054175
申请日：2019-10-02
Applicant: INTEL CORPORATION
Inventor： HAMIDOVIC, Damir , BUCKEL, Tobias , KLINKAN, Alexander , KUTTNER, Franz , MARKOVIC, Jovan , PREYLER, Peter
Abstract: Techniques are disclosed to provide a data dependent delay for a multi-phase transmitter architectures. These techniques include identifying a current segment occupied by a symbol associated with in-phase (I) and quadrature phase (Q) data within a data constellation based upon the number of phases used. Once the segment is identified, vector components are calculated as a function of the segment used to re-map the symbol within the constellation defined in accordance with the number of phases. The data delay may be performed in the baseband or at the RF rate to time-align local oscillator clocks with the delayed data, which is represented as the calculated vector components, for transmission. Further modifications to the RF-DAC operation to facilitate operation with the multi-phase system are also disclosed.
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公开(公告)号：WO2020205094A1
公开(公告)日：2020-10-08
申请号：PCT/US2020/019778
申请日：2020-02-26
Applicant: INTEL CORPORATION
Inventor： KUTTNER, Franz
Abstract: A digital-to-analog converter is provided. The digital-to-analog converter includes a plurality of digital-to-analog converter cells coupled to an output node of the digital-to-analog converter. At least one of the plurality of digital-to-analog converter cells includes a capacitive element configured to provide an analog output signal of the digital-to-analog converter cell to the output node. Further, the at least one of the plurality of digital-to-analog converter cells includes an inverter circuit coupled to the capacitive element. The inverter circuit is configured to generate an inverter signal for the capacitive element based on an oscillation signal. The at least one of the plurality of digital-to-analog converter cells additionally includes a resistive element coupled to the inverter circuit and the capacitive element. A resistance of the resistive element is at least 50Ω.
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Patent Agency Ranking3.发明申请
公开(公告)号：WO2020139449A1
公开(公告)日：2020-07-02
申请号：PCT/US2019/057574
申请日：2019-10-23
Applicant: INTEL CORPORATION
Inventor： KUTTNER, Franz
Abstract: CDAC (Capacitive DAC (Digital-to-Analog Converter) unit cells and RFDACs (Radio Frequency DACs) employing such CDAC unit cells are disclosed that can be employed for mmWave (millimeter wave) communication are disclosed. One example CDAC unit cell comprises: four capacitors connected in pairs to two differential outputs of the CDAC unit cell; and four logic gates, wherein each logic gate of the four logic gates is configured to receive an associated clock signal of four different clock signals and an associated enable signal of four different enable signals, and wherein each logic gate of the four logic gates is configured to trigger an associated pulse from an associated capacitor of the four capacitors based on the associated clock signal and the associated enable signal of that logic gate.
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公开(公告)号：WO2020139437A1
公开(公告)日：2020-07-02
申请号：PCT/US2019/054177
申请日：2019-10-02
Applicant: INTEL CORPORATION
Inventor： KUTTNER, Franz
Abstract: A digital-to-analog converter (DAC) linearization system can include a DAC configured to generate an analog output signal based on a digital input signal, a detector configured to detect noise on a supply voltage and generate a noise detection signal based on the detected noise, and a compensator that is configured to generate a compensated analog signal based on the analog output signal and the noise detection signal.
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公开(公告)号：WO2020197633A1
公开(公告)日：2020-10-01
申请号：PCT/US2020/016026
申请日：2020-01-31
Applicant: INTEL IP CORPORATION , INTEL CORPORATION
Inventor： PONTON, Davide , KALCHER, Michael , PAUSSA, Alan , THALLER, Edwin , KUTTNER, Franz , GRUBER, Daniel
Abstract: A radio frequency digital-to-analog converter (RFDAC) circuit includes an RFDAC array circuit including an array of cells arranged into a plurality of segments. Each segment of the plurality of segments is configured to process input data signals. The RFDAC array circuit is configured to process an input data based on activating a set of segments of the plurality of segments, forming a set of active segments, and when the sign of the input data is changed, deactivate a partially active segment of the set of active segments and activate a sign change segment within the RFDAC array circuit. The sign change segment includes a segment within the plurality of segments of the RFDAC array circuit that is different from the set of active segments.
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6.发明申请
公开(公告)号：WO2020139450A1
公开(公告)日：2020-07-02
申请号：PCT/US2019/057873
申请日：2019-10-24
Applicant: INTEL CORPORATION
Inventor： KUTTNER, Franz
Abstract: High efficiency amplitude DACs and RFDACs employing such amplitude DACs are discussed. One exemplary embodiment is a DAC comprising a plurality of DAC stages, wherein each DAC stage of the plurality of DAC stages is associated with a respective predetermined voltage of a plurality of predetermined voltages, wherein each DAC stage of the plurality of DAC stages can receive a digital signal at the respective predetermined voltage associated with that DAC stage when the respective predetermined voltage of that DAC stage is a selected predetermined voltage, wherein the selected predetermined voltage is based on an amplitude of the digital signal, and wherein each DAC stage of the plurality of DAC stages can generate a respective analog signal associated with that DAC stage based on the digital signal received at that DAC stage when the respective predetermined voltage of that DAC stage is the selected predetermined voltage.
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公开(公告)号：WO2015108620A1
公开(公告)日：2015-07-23
申请号：PCT/US2014/066526
申请日：2014-11-20
Applicant: INTEL CORPORATION
Inventor： KUTTNER, Franz
CPC classification number: H03F3/45071 , G05F1/575 , H03F3/45183 , H03F2203/45652
Abstract: Representative implementations of devices and techniques provide a regulator having a high regulation speed and low noise across a wide frequency range. A pass through device outputs a regulated voltage based on a control signal output by an error amplifier. The control signal is boosted via a regulated boost signal.
Abstract translation: 器件和技术的代表性实现提供了在宽频率范围内具有高调节速度和低噪声的调节器。 通过装置根据由误差放大器输出的控制信号输出调节电压。 控制信号通过调节的升压信号升压。
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