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    BACKWARD-COMPATIBLE EXTENDED SIZE NODE LID TO PROVIDE ADDITIONAL REAL ESTATE FOR FUTURE FUNCTIONALITY
    1.
    发明申请
    BACKWARD-COMPATIBLE EXTENDED SIZE NODE LID TO PROVIDE ADDITIONAL REAL ESTATE FOR FUTURE FUNCTIONALITY 审中-公开

    公开(公告)号：WO2020081797A1

    公开(公告)日：2020-04-23

    申请号：PCT/US2019/056716

    申请日：2019-10-17

    Applicant: ARRIS ENTERPRISES LLC

    Inventor： AL-BANNA, Ayham

    IPC: G02B6/44 ,  H02G3/14

    Abstract: A fiber optic node (100) includes an electronics equipment enclosure (120). The electronics equipment enclosure (120) includes a lid (135) and a base (140) defining an overall interior space (145) of the electronics equipment enclosure. The lid (135) includes a lid top (137) and a lid mating surface (138) to contact and overlap a base mating surface (143) of the base (140) to close the electronics equipment enclosure (120). The lid (135) further includes at least one lid side wall (176) extending away from the lid top (137). The at least one lid side wall (176) includes at least one protruding lid side wall (175) extending outwards to project beyond the lid mating surface (138). The base (140) includes a base bottom (142) and at least one base side wall (141D) extending away from the base bottom (142). The base (140) further includes a base mating surface (143) to contact and overlap the lid mating surface (138) of the lid (135) to close the electronics equipment enclosure (120).

    INTRA MODE JVET CODING
    3.
    发明申请
    INTRA MODE JVET CODING 审中-公开

    公开(公告)号：WO2019023200A1

    公开(公告)日：2019-01-31

    申请号：PCT/US2018/043438

    申请日：2018-07-24

    Applicant: ARRIS ENTERPRISES LLC

    Inventor： YU, Yue ,  WANG, Limin

    IPC: H04N19/463 ,  H04N19/593 ,  H04N19/13 ,  H04N19/176

    Abstract: A method of partitioning a video coding block for JVET, wherein a set of MPMs includes a set of other than 6 intra prediction coding modes and can be encoded using truncated unary binarization, 16 selected intra prediction coding modes can be encoded used 4 bits of fixed length code and remaining non-selected coding modes can be encoded using truncated binary coding and wherein a JVET coding tree unit can be coded as a root node in a quadtree plus binary tree (QTBT) structure that can have a quadtree branching from the root node and binary trees branching from each of the quadtree's leaf nodes using asymmetric binary partitioning to split a coding unit represented by a quadtree leaf node into child nodes, representing the child nodes as leaf nodes in a binary tree branching from the quadtree leaf node.

    UNEQUAL WEIGHT PLANAR PREDICTION
    5.
    发明申请
    UNEQUAL WEIGHT PLANAR PREDICTION 审中-公开

    公开(公告)号：WO2018125988A1

    公开(公告)日：2018-07-05

    申请号：PCT/US2017/068682

    申请日：2017-12-28

    Applicant: ARRIS ENTERPRISES LLC

    Inventor： PANUSOPONE, Krit ,  YU, Yue ,  HONG, Seungwook ,  WANG, Limin

    IPC: H04N19/593 ,  H04N19/105 ,  H04N19/176 ,  H04N19/11 ,  H04N19/136

    Abstract: A method of decoding JVET video includes receiving a bitstream and calculating a final planar prediction in planar mode to predict pixel values for a current coding block. The final planar prediction may rely on using unequal weights applied to each of a horizontal and vertical predictor, where such predictors may be generated by interpolating neighboring pixels for each predicted pixel within a coding block. The computation may be made more accurate by deriving a value for a bottom right neighboring pixel.

    AMPLIFIER WITH POWER DISSIPATION REDUCTION USING SINGLE RADIO FREQUENCY DIGITAL-TO-ANALOG CONVERTER
    6.
    发明申请
    AMPLIFIER WITH POWER DISSIPATION REDUCTION USING SINGLE RADIO FREQUENCY DIGITAL-TO-ANALOG CONVERTER 审中-公开

    公开(公告)号：WO2018118749A1

    公开(公告)日：2018-06-28

    申请号：PCT/US2017/066947

    申请日：2017-12-18

    Applicant: ARRIS ENTERPRISES LLC

    Inventor： SCHEMMANN, Marcel F. ,  LESHEM, Ido

    IPC: H03F1/32 ,  H03F3/189 ,  H03F1/02 ,  H03F3/68

    Abstract: The disclosed system and method provide for a CATV power amplifier (560) in which power dissipation may be reduced by dynamically adjusting the amplifier bias such that the bias is high only when high peak output signals need to be produced. By combining a bias control signal and an RF data signal into a single signal produced by a single DA converter (540), the disclosed examples require fewer DA converters and a need to synchronize DA converters to produce each of the signals individually is eliminated. A low frequency signal may be added to the RF band to find an optimum compromise between positive and negative peak excursions produced by the amplifier such that an overall reduction in bias may be achieved.

    AGRREGATOR-BASED COST-OPTIMIZED COMMUNICATIONS TOPOLOGY FOR A POINT-TO-MULTIPOINT NETWORK
    7.
    发明申请
    AGRREGATOR-BASED COST-OPTIMIZED COMMUNICATIONS TOPOLOGY FOR A POINT-TO-MULTIPOINT NETWORK 审中-公开
    基于AGRREGATOR的成本优化的点对多点网络通信拓扑

    公开(公告)号：WO2017151395A1

    公开(公告)日：2017-09-08

    申请号：PCT/US2017/019196

    申请日：2017-02-23

    Applicant: ARRIS ENTERPRISES LLC

    Inventor： MARICEVIC, Zoran ,  SCHEMMANN, Marcel F. ,  MUTALIK, Venkatesh G. ,  SUN, Zhijian

    IPC: H04B10/2575 ,  H04J14/02

    Abstract: An optical combiner for a communications network transmitting both upstream signals and a downstream optical signal. The communications network includes an array of amplifiers, each receiving a respective instance of the downstream optical signal. The output of each amplifier is split among a plurality of ports in a first splitter/combiner unit. The first splitter/combiner unit transmits the amplified downstream optical signal to respective second splitter/combiner units.

    Abstract translation: 一种用于通信网络的光组合器，用于传输上游信号和下游光信号。 通信网络包括放大器阵列，每个放大器接收下游光学信号的相应实例。 每个放大器的输出在第一分路器/组合器单元的多个端口之间分配。 第一分路器/组合器单元将放大的下游光信号传送到相应的第二分路器/组合器单元。

    SYSTEM FOR RESHAPING AND CODING HIGH DYNAMIC RANGE AND WIDE COLOR GAMUT SEQUENCES
    8.
    发明申请
    SYSTEM FOR RESHAPING AND CODING HIGH DYNAMIC RANGE AND WIDE COLOR GAMUT SEQUENCES 审中-公开
    用于改变和编码高动态范围和宽彩色游戏序列的系统

    公开(公告)号：WO2017053852A1

    公开(公告)日：2017-03-30

    申请号：PCT/US2016/053521

    申请日：2016-09-23

    Applicant: ARRIS ENTERPRISES LLC

    Inventor： MINOO, Koohyar ,  BAYLON, David M. ,  GU, Zhouye ,  YU, Yue ,  LUTHRA, Ajay

    IPC: H04N19/98 ,  H04N19/70 ,  G06T5/00

    CPC classification number: H04N19/124 ,  G06T5/007 ,  G06T2207/20208 ,  H04N19/174 ,  H04N19/177 ,  H04N19/186 ,  H04N19/44 ,  H04N19/70 ,  H04N19/98

    Abstract: A video data encoder generates a first metadata structure to describe one or more transfer functions to be applied by a decoder to reshape decoded video data into video data. The encoder segments a transfer function relative to P pivot points. It then allocates P cells in the metadata structure for storing the P pivot points. Each transfer function segment is fitted to a respective equation having N coefficients based on the order of the equation. The encoder allocates N+1 cells for each pivot point except for the P th pivot point and stores the number N in the first cell and the N coefficients in the remaining cells. The encoder generates a second metadata structure, associated with a video data set, that includes data identifying the transfer function to be applied to the video data set. The encoder encodes the video data including the first and second metadata structures.

    Abstract translation: 视频数据编码器生成第一元数据结构以描述由解码器应用的一个或多个传送函数，以将解码的视频数据重新形成视频数据。 编码器相对于P个枢轴点分段传递函数。 然后，它将P细胞分配到用于存储P个枢轴点的元数据结构中。 每个传递函数段被拟合到具有基于等式​​的顺序的N个系数的相应等式。 编码器为除了第P个枢轴点之外的每个枢轴点分配N + 1个单元，并将数量N存储在第一单元中，并将剩余单元中的N个系数存储。 编码器生成与视频数据集相关联的第二元数据结构，其包括标识要应用于视频数据集的传递函数的数据。 编码器对包括第一和第二元数据结构的视频数据进行编码。

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