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    FRACTIONAL-WORD WRITABLE ARCHITECTED REGISTER FOR DIRECT ACCUMULATION OF MISALIGNED DATA
    1.
    发明申请
    FRACTIONAL-WORD WRITABLE ARCHITECTED REGISTER FOR DIRECT ACCUMULATION OF MISALIGNED DATA 审中-公开
    用于直接累积错误数据的分数字可写体系结构寄存器

    公开(公告)号：WO2006084289A2

    公开(公告)日：2006-08-10

    申请号：PCT/US2006006994

    申请日：2006-02-03

    Applicant: QUALCOMM INC ,  BRIDGES JEFFREY TODD ,  AUGSBURG VICTOR ROBERTS ,  DIEFFENDERFER JAMES NORRIS ,  SARTORIUS THOMAS ANDREW

    Inventor： BRIDGES JEFFREY TODD ,  AUGSBURG VICTOR ROBERTS ,  DIEFFENDERFER JAMES NORRIS ,  SARTORIUS THOMAS ANDREW

    IPC: G06F9/312

    CPC classification number: G06F9/30043

    Abstract: One or more architected registers in a processor are fractional-word writable, and data from plural misaligned memory access operations are assembled directly in an architected register, without first assembling the data in a fractional-word writable, non-architected register and then transferring it to the architected register. In embodiments where a general-purpose register file utilizes register renaming or a reorder buffer, data from plural misaligned memory access operations are assembled directly in a fractional-word writable architected register, without the need to fully exception check both misaligned memory access operations before performing the first memory access operation.

    Abstract translation: 处理器中的一个或多个架构寄存器是分数字可写入的，并且来自多个未对齐存储器访问操作的数据直接组装在架构寄存器中，而不首先将数据组装成分数字可写，非架构寄存器，然后将其传送 到架构的注册表。 在通用寄存器文件利用寄存器重命名或重排缓冲器的实施例中，来自多个未对准的存储器访问操作的数据直接组装在分数字可写架构寄存器中，而不需要在执行之前完全异常检查未对齐的存储器访问操作 第一次内存访问操作。

    LATENCY INSENSITIVE FIFO SIGNALING PROTOCOL
    2.
    发明申请
    LATENCY INSENSITIVE FIFO SIGNALING PROTOCOL 审中-公开
    LATENCY INSENSITIVE FIFO信号协议

    公开(公告)号：WO2006124410A3

    公开(公告)日：2007-09-20

    申请号：PCT/US2006017899

    申请日：2006-05-08

    Applicant: QUALCOMM INC ,  DOCKSER KENNETH ALAN ,  AUGSBURG VICTOR ROBERTS ,  DIEFFENDERFER JAMES NORRIS ,  BRIDGES JEFFREY TODD ,  CLANCY ROBERT DOUGLAS ,  SARTORIUS THOMAS ANDREW

    Inventor： DOCKSER KENNETH ALAN ,  AUGSBURG VICTOR ROBERTS ,  DIEFFENDERFER JAMES NORRIS ,  BRIDGES JEFFREY TODD ,  CLANCY ROBERT DOUGLAS ,  SARTORIUS THOMAS ANDREW

    IPC: G06F13/38

    CPC classification number: G06F13/4059 ,  G06F5/06 ,  G06F2205/126

    Abstract: Data from a source domain (311 ) operating at a first data rate is transferred to a FIFO (319) in another domain (313) operating at a different data rate. The FIFO (319) buffers data before transfer to a sink for further processing or storage. A source side counter (325) tracks space available in the FIFO. In disclosed examples, the initial counter value corresponds to FIFO depth. The counter (325) decrements in response to a data ready signal from the source domain (311)1 without delay. The counter (325) increments in response to signaling from the sink domain (313) of a read of data off the FIFO (319). Hence, incrementing is subject to the signaling latency between domains. The source (315) may send one more beat of data when the counter (325) indicates the FIFO (319) is full. The last beat of data is continuously sent from the source until it is indicated that a FIFO position became available; effectively providing one o more FIFO positions.

    Abstract translation: 来自以第一数据速率运行的源域（311）的数据被传送到以不同数据速率工作的另一域（313）中的FIFO（319）。 FIFO（319）在传输到宿之前缓冲数据以进一步处理或存储。 源侧计数器（325）跟踪FIFO中可用的空间。 在所公开的示例中，初始计数器值对应于FIFO深度。 计数器（325）响应于来自源域（311）1的数据就绪信号而没有延迟地递减。 计数器（325）响应于来自接收器域（313）的从FIFO（319）读取的数据的信令而递增。 因此，增量受到域之间的信令等待时间的限制。 当计数器（325）指示FIFO（319）已满时，源（315）可以再发送一个数据节拍。 数据的最后一次节拍从源头连续发送到指示FIFO位置可用为止; 有效提供一个以上的FIFO位置。

    UNALIGNED MEMORY ACCESS PREDICTION
    3.
    发明申请
    UNALIGNED MEMORY ACCESS PREDICTION 审中-公开

    公开(公告)号：WO2006089194A3

    公开(公告)日：2007-03-29

    申请号：PCT/US2006005782

    申请日：2006-02-16

    Applicant: QUALCOMM INC ,  BRIDGES JEFFREY TODD ,  AUGSBURG VICTOR ROBERTS ,  DIEFFENDERFER JAMES NORRIS ,  SARTORIUS THOMAS ANDREW

    Inventor： BRIDGES JEFFREY TODD ,  AUGSBURG VICTOR ROBERTS ,  DIEFFENDERFER JAMES NORRIS ,  SARTORIUS THOMAS ANDREW

    IPC: G06F9/312 ,  G06F9/318 ,  G06F9/38

    CPC classification number: G06F9/30043 ,  G06F9/30145 ,  G06F9/30189 ,  G06F9/3824 ,  G06F9/3832 ,  G06F9/3855

    Abstract: In an instruction execution pipeline, the misalignment of memory access instructions is predicted. Based on the prediction, an additional micro-operation is generated in the pipeline prior to the effective address generation of the memory access instruction. The additional micro-operation accesses the memory falling across a predetermined address boundary. Predicting the misalignment and generating a micro-operation early in the pipeline ensures that sufficient pipeline control resources are available to generate and track the additional micro-operation, avoiding a pipeline flush if the resources are not available at the time of effective address generation. The misalignment prediction may employ known conditional branch prediction techniques, such as a flag, a bimodal counter, a local predictor, a global predictor, and combined predictors. A misalignment predictor may be enabled or biased by a memory access instruction flag or misaligned instruction type.

    Abstract translation: 在指令执行流水线中，预测存储器访问指令的未对准。 基于该预测，在存储器访问指令的有效地址生成之前在流水线中生成附加的微操作。 附加的微操作访问落在预定地址边界上的存储器。 预测未对准并在管道早期生成微操作确保足够的流水线控制资源可用于生成和跟踪额外的微操作，如果资源在有效地址生成时不可用，则避免管道冲洗。 不对准预测可以使用已知的条件分支预测技术，例如标志，双模计数器，局部预测器，全局预测器和组合预测器。 未对准预测器可能被存储器访问指令标志或未对准指令类型使能或偏置。

    LATENCY INSENSITIVE FIFO SIGNALING PROTOCOL
    4.
    发明申请
    LATENCY INSENSITIVE FIFO SIGNALING PROTOCOL 审中-公开
    LATENCY INSENSITIVE FIFO信号协议

    公开(公告)号：WO2006124410A2

    公开(公告)日：2006-11-23

    申请号：PCT/US2006/017899

    申请日：2006-05-08

    Applicant: QUALCOMM INCORPORATED ,  DOCKSER, Kenneth, Alan ,  AUGSBURG, Victor, Roberts ,  DIEFFENDERFER, James, Norris ,  BRIDGES, Jeffrey, Todd ,  CLANCY, Robert, Douglas ,  SARTORIUS, Thomas, Andrew

    Inventor： DOCKSER, Kenneth, Alan ,  AUGSBURG, Victor, Roberts ,  DIEFFENDERFER, James, Norris ,  BRIDGES, Jeffrey, Todd ,  CLANCY, Robert, Douglas ,  SARTORIUS, Thomas, Andrew

    IPC: G06F13/38

    CPC classification number: G06F13/4059 ,  G06F5/06 ,  G06F2205/126

    Abstract: Data from a source domain operating at a first data rate is transferred to a FIFO in another domain operating at a different data rate. The FIFO buffers data before transfer to a sink for further processing or storage. A source side counter tracks space available in the FIFO. In disclosed examples, the initial counter value corresponds to FIFO depth. The counter decrements in response to a data ready signal from the source domain, without delay. The counter increments in response to signaling from the sink domain of a read of data off the FIFO. Hence, incrementing is subject to the signaling latency between domains. The source may send one more beat of data when the counter indicates the FIFO is full. The last beat of data is continuously sent from the source until it is indicated that a FIFO position became available; effectively providing one more FIFO position.

    Abstract translation: 来自以第一数据速率运行的源域的数据被传送到以不同数据速率操作的另一域中的FIFO。 FIFO在传输到接收器之前缓冲数据以进一步处理或存储。 源侧计数器跟踪FIFO中可用的空间。 在所公开的示例中，初始计数器值对应于FIFO深度。 响应于来自源域的数据就绪信号，计数器无延迟地递减。 计数器响应来自接收器域的信令从FIFO的数据读取而递增。 因此，增量受到域之间的信令等待时间的限制。 当计数器指示FIFO已满时，源可能再发送一次数据。 数据的最后一次节拍从源头连续发送到指示FIFO位置可用为止; 有效提供一个FIFO位置。

    UNALIGNED MEMORY ACCESS PREDICTION
    5.
    发明申请
    UNALIGNED MEMORY ACCESS PREDICTION 审中-公开

    公开(公告)号：WO2006089194A2

    公开(公告)日：2006-08-24

    申请号：PCT/US2006/005782

    申请日：2006-02-16

    Applicant: QUALCOMM INCORPORATED ,  BRIDGES, Jeffrey Todd ,  AUGSBURG, Victor Roberts ,  DIEFFENDERFER, James Norris ,  SARTORIUS, Thomas Andrew

    Inventor： BRIDGES, Jeffrey Todd ,  AUGSBURG, Victor Roberts ,  DIEFFENDERFER, James Norris ,  SARTORIUS, Thomas Andrew

    CPC classification number: G06F9/30043 ,  G06F9/30145 ,  G06F9/30189 ,  G06F9/3824 ,  G06F9/3832 ,  G06F9/3855

    Abstract: In an instruction execution pipeline, the misalignment of memory access instructions is predicted. Based on the prediction, an additional micro-operation is generated in the pipeline prior to the effective address generation of the memory access instruction. The additional micro-operation accesses the memory falling across a predetermined address boundary. Predicting the misalignment and generating a micro-operation early in the pipeline ensures that sufficient pipeline control resources are available to generate and track the additional micro-operation, avoiding a pipeline flush if the resources are not available at the time of effective address generation. The misalignment prediction may employ known conditional branch prediction techniques, such as a flag, a bimodal counter, a local predictor, a global predictor, and combined predictors. A misalignment predictor may be enabled or biased by a memory access instruction flag or misaligned instruction type.

    Abstract translation: 在指令执行流水线中，预测存储器访问指令的未对准。 基于该预测，在存储器访问指令的有效地址生成之前在流水线中生成附加的微操作。 附加的微操作访问落在预定地址边界上的存储器。 预测未对准并在管道早期生成微操作确保足够的流水线控制资源可用于生成和跟踪附加的微操作，如果资源在有效地址生成时不可用，则避免管道冲洗。 不对准预测可以使用已知的条件分支预测技术，例如标志，双模计数器，局部预测器，全局预测器和组合预测器。 未对准预测器可能被存储器访问指令标志或未对准指令类型使能或偏置。

    GLOBAL MODIFIED INDICATOR TO REDUCE POWER CONSUMPTION ON CACHE MISS
    6.
    发明申请
    GLOBAL MODIFIED INDICATOR TO REDUCE POWER CONSUMPTION ON CACHE MISS 审中-公开
    全球改装指标，以减少高速缓存的功耗

    公开(公告)号：WO2006102665A3

    公开(公告)日：2007-04-26

    申请号：PCT/US2006011172

    申请日：2006-03-23

    Applicant: QUALCOMM INC ,  SARTORIUS THOMAS ANDREW ,  AUGSBURG VICTOR ROBERTS ,  DIEFFENDERFER JAMES NORRIS

    Inventor： SARTORIUS THOMAS ANDREW ,  AUGSBURG VICTOR ROBERTS ,  DIEFFENDERFER JAMES NORRIS

    IPC: G06F12/08

    CPC classification number: G06F12/0804 ,  G06F2212/1028 ,  Y02D10/13

    Abstract: A processor includes a cache memory having at least one entry managed according to a copy-back algorithm. A global modified indicator (GMI) indicates whether any copy-back entry in the cache contains modified data. On a cache miss, if the GMI indicates that no copy-back entry in the cache contains modified data, data fetched from memory are written to the selected entry without first reading the entry. In a banked cache, two or more bank-GMIs may be associated with two or more banks. In an n-way set associative cache, n set-GMIs may be associated with the n sets. Suppressing the read to determine if the copy-back cache entry contains modified data improves processor performance and reduces power consumption.

    Abstract translation: 处理器包括具有根据回写算法管理的至少一个条目的高速缓冲存储器。 全局修改指示符（GMI）指示高速缓存中是否有任何复制条目包含修改的数据。 在缓存未命中时，如果GMI指示高速缓存中没有复制条目包含已修改的数据，则从内存中读取的数据将被写入所选条目，而无需先读入条目。 在一个银行缓存中，两个或多个银行GMI可以与两个或更多个银行相关联。 在n路集合关联高速缓存中，n个集合GMI可以与n个集合相关联。 禁止读取以确定复制缓存条目是否包含修改的数据是否能够提高处理器性能并降低功耗。

    TLB LOCK INDICATOR
    7.
    发明申请
    TLB LOCK INDICATOR 审中-公开
    TLB锁定指示器

    公开(公告)号：WO2007024937A1

    公开(公告)日：2007-03-01

    申请号：PCT/US2006/032902

    申请日：2006-08-22

    Applicant: QUALCOMM Incorporated ,  AUGSBURG, Victor Roberts ,  DIEFFENDERFER, James Norris ,  BRIDGES, Jeffrey Todd ,  SARTORIUS, Thomas Andrew

    Inventor： AUGSBURG, Victor Roberts ,  DIEFFENDERFER, James Norris ,  BRIDGES, Jeffrey Todd ,  SARTORIUS, Thomas Andrew

    IPC: G06F12/12 ,  G06F12/10

    CPC classification number: G06F12/1027 ,  G06F12/126 ,  G06F2212/681

    Abstract: A processor includes a hierarchical Translation Lookaside Buffer (TLB) comprising a Level-1 TLB and a small, high-speed Level-0 TLB. Entries in the L0 TLB replicate entries in the L1 TLB. The processor first accesses the L0 TLB in an address translation, and access the L1 TLB if a virtual address misses in the L0 TLB. When the virtual address hits in the L1 TLB, the virtual address, physical address, and page attributes are written to the L0 TLB, replacing an existing entry if the L0 TLB is full. The entry may be locked against replacement in the L0 TLB in response to an L0 Lock (L0L) indicator in the L1 TLB entry. Similarly, in a hardware-managed L1 TLB, entries may be locked against replacement in response to an L1 Lock (L1L) indicator in the corresponding page table entry.

    Abstract translation: 处理器包括包括Level-1 TLB和小的高速Level-0 TLB的分级翻译后备缓冲器（TLB）。 L0 TLB中的条目复制L1 TLB中的条目。 处理器首先在地址转换中访问L0 TLB，如果在L0 TLB中虚拟地址丢失，则访问L1 TLB。 当虚拟地址在L1 TLB中时，虚拟地址，物理地址和页面属性被写入L0 TLB，如果L0 TLB已满，则替换现有条目。 响应于L1 TLB条目中的L0锁定（L0L）指示灯，该条目可能被锁定在L0 TLB中。 类似地，在硬件管理的L1 TLB中，可以响应于相应页表条目中的L1锁定（L1L）指示符来锁定条目以替代。

    UPDATING MULTIPLE LEVELS OF TRANSLATION LOOKASIDE BUFFERS (TLBS) FIELD
    10.
    发明申请
    UPDATING MULTIPLE LEVELS OF TRANSLATION LOOKASIDE BUFFERS (TLBS) FIELD 审中-公开
    更新多层次的翻译LOOKASIDE BUFFERS（TLBS）领域

    公开(公告)号：WO2007048134A1

    公开(公告)日：2007-04-26

    申请号：PCT/US2006/060134

    申请日：2006-10-20

    Applicant: QUALCOMM INCORPORATED ,  AUGSBURG, Victor Roberts ,  SARTORIUS, Thomas Andrew ,  DIEFFENDERFER, James Norris ,  BRIDGES, Jeffrey Todd

    Inventor： AUGSBURG, Victor Roberts ,  SARTORIUS, Thomas Andrew ,  DIEFFENDERFER, James Norris ,  BRIDGES, Jeffrey Todd

    IPC: G06F12/10

    CPC classification number: G06F12/1027 ,  G06F2212/681 ,  G06F2212/684

    Abstract: An apparatus includes a memory configured to store data, a lower level TLB, an upper level TLB, and a TLB controller. The lower level TLB and the upper level TLB are configured to store a plurality of entries, each of the entries containing an address translation information that allows a virtual address to be translated into a corresponding physical address. The TLB controller retrieves from a page table in the memory an address translation information for a desired virtual address, if the desired virtual address generates a TLB miss from the lower level TLB and from the upper level TLB, Using a single TLB write instruction, the TLB controller updates both the lower level TLB and the upper level TLB by writing the address translation information, retrieved from the page table, into the lower level TLB as well as into the upper level TLB.

    Abstract translation: 一种装置包括被配置为存储数据的存储器，较低级TLB，上级TLB和TLB控制器。 下级TLB和上级TLB被配置为存储多个条目，每个条目包含允许将虚拟地址转换成对应的物理地址的地址转换信息。 如果所需的虚拟地址从较低级别的TLB和上级TLB生成TLB未命中，则TLB控制器从存储器中的页表中检索所需虚拟地址的地址转换信息。使用单个TLB写指令， TLB控制器通过将从页表中检索的地址转换信息写入下级TLB以及上级TLB来更新下级TLB和上级TLB。

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