REGULATED VOLTAGE DUAL-WIRE-TYPE DETECTOR
    1.
    发明申请
    REGULATED VOLTAGE DUAL-WIRE-TYPE DETECTOR 审中-公开
    调节电压双线型检测器

    公开(公告)号:WO1992007426A1

    公开(公告)日:1992-04-30

    申请号:PCT/FR1991000814

    申请日:1991-10-17

    Inventor: TELEMECANIQUE

    CPC classification number: G01D21/00 H03K17/951 Y10T307/766 Y10T307/773

    Abstract: Detector comprising a sensor and a processing circuit connected to a load by means of two wires. Two switches (I1, I2) are arranged in series in a switching circuit leg (21), the ends of which (C, D) are connected to the detector terminals and the middle point (S) to a terminal (F) of the processing circuit. When operating (I1) is conductive and (I2) determines a parallel regulation of the voltage (V) at the processing circuit (12) terminals; when in rest position, (I1) determines a series regulation of the voltage, while (I2) is blocked.

    FSK PERMUTATION MODULATION
    2.
    发明申请
    FSK PERMUTATION MODULATION 审中-公开
    FSK离心调制

    公开(公告)号:WO1996004740A1

    公开(公告)日:1996-02-15

    申请号:PCT/CA1995000424

    申请日:1995-07-13

    CPC classification number: H04L27/28

    Abstract: A spectral encoding-decoding system for encoding a sequence of N data bits where N is a predetermined integer, into an information signal to be transmitted on a communication medium and for decoding the information signal transmitted on the communication signal into an estimated sequence of N data bits. The system comprises an encoder and a decoder. The encoder receives the sequence of N data bits, encodes the sequence into the information signal, and emits the information on the communication medium. The decoder receives the information signal transmitted on the communication medium, decodes the information signal and transmits the estimated sequence of N data bits. The system is compact, simple and does not require large calculating capabilities. This system is useful for communication between two computers on any type of communication medium.

    Abstract translation: 一种频谱编码解码系统,用于将N个预定整数的N个数据比特序列编码成要在通信介质上发送的信息信号,并将通信信号上发送的信息信号解码成N个数据的估计序列 位。 该系统包括编码器和解码器。 编码器接收N个数据比特序列,将序列编码成信息信号,并在通信介质上发送信息。 解码器接收在通信介质上发送的信息信号,对信息信号进行解码并发送估计的N个数据比特序列。 该系统紧凑,简单,不需要较大的计算能力。 该系统对于任何类型的通信介质上的两台计算机之间的通信是有用的。

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