公开(公告)号：WO2023075867A1

公开(公告)日：2023-05-04

申请号：PCT/US2022/034428

申请日：2022-06-22

Applicant: EDGECORTIX PTE. LTD. ,  EDGECORTIX CORPORATION

Inventor： NEZ, Nikolay ,  KHAVIN, Oleg ,  AHMED, Tanvir ,  HUTHMANN, Jens ,  DASGUPTA, Sakyasingha

IPC: G06N3/063

Abstract: Neural network hardware acceleration data parallelism is performed by an integrated circuit including a plurality of memory banks, each memory bank among the plurality of memory banks configured to store values and to transmit stored values, a plurality of computation units, each computation unit among the plurality of computation units including a processor including circuitry configured to perform a mathematical operation on an input data value and a weight value to produce a resultant data value, and a computation controller configured to cause a value transmission to be received by more than one computation unit or memory bank.

公开(公告)号：WO2022147518A1

公开(公告)日：2022-07-07

申请号：PCT/US2022/011071

申请日：2022-01-04

Applicant: EDGECORTIX PTE. LTD. ,  EDGECORTIX CORPORATION

Inventor： NEZ, Nikolay ,  ZOHOURI, Hamid Reza ,  KHAVIN, Oleg ,  VILCHEZ, Antonio Tomas Nevado ,  DASGUPTA, Sakyasingha

IPC: G06N3/063 ,  G06F17/15 ,  G06N5/04

Abstract: Neural network inference may be performed by configuration of a device including an accumulation memory, a plurality of convolution modules configured to perform mathematical operations on input values, a plurality of adder modules configured to sum values output from the plurality of convolution modules, and a plurality of convolution output interconnects connecting the plurality of convolution modules, the plurality of adder modules, and the accumulation memory. The accumulation memory is an accumulation memory allocation of a writable memory block having a reconfigurable bank width, and each bank of the accumulation memory allocation is a virtual combination of consecutive banks of the writable memory block.