公开(公告)号：WO2008124455A3

公开(公告)日：2008-12-24

申请号：PCT/US2008059172

申请日：2008-04-02

Applicant: INTEL CORP ,  ILLIKKAL RAMESH KUMAR ,  IYER RAVISHANKAR ,  MOSES JAIDEEP ,  NEWELL DON ,  FOSSUM TRYGGVE

Inventor： ILLIKKAL RAMESH KUMAR ,  IYER RAVISHANKAR ,  MOSES JAIDEEP ,  NEWELL DON ,  FOSSUM TRYGGVE

IPC: G06F1/26

CPC classification number: G06F9/5077 ,  G06F9/5094 ,  G06F2209/504 ,  Y02D10/22 ,  Y02D10/36

Abstract: A method and apparatus for throttling power and/or performance of processing elements based on a priority of software entities is herein described. Priority aware power management logic receives priority levels of software entities and modifies operating points of processing elements associated with the software entities accordingly. Therefore, in a power savings mode, processing elements executing low priority applications/tasks are reduced to a lower operating point, i.e. lower voltage, lower frequency, throttled instruction issue, throttled memory accesses, and/or less access to shared resources. In addition, utilization logic potentially trackes utilization of a resource per priority level, which allows the power manager to determine operating points based on the affect of each priority level on each other from the perspective of the resources themselves. Moreover, a software entity itself may assign operating points, which the power manager enforces.

Abstract translation: 这里描述了一种基于软件实体的优先级来节制处理元件的功率和/或性能的方法和装置。 优先级感知功率管理逻辑接收软件实体的优先级，并相应地修改与软件实体相关联的处理元件的工作点。 因此，在省电模式中，执行低优先级应用/任务的处理元件被减少到较低的工作点，即较低的电压，较低的频率，节流的指令问题，节流的存储器访问和/或较少的对共享资源的访问。 此外，利用逻辑潜在地追踪每个优先级的资源的利用率，这允许电力管理者从资源本身的角度基于彼此的每个优先级的影响来确定工作点。 此外，软件实体本身可以分配功率管理器执行的操作点。

公开(公告)号：WO2006014254A1

公开(公告)日：2006-02-09

申请号：PCT/US2005/022773

申请日：2005-06-25

Applicant: INTEL CORPORATION ,  FOSSUM, Tryggve ,  CHRYSOS, George ,  DUTTON, Todd

Inventor： FOSSUM, Tryggve ,  CHRYSOS, George ,  DUTTON, Todd

IPC: G06F15/76

CPC classification number: G06F9/3836 ,  G06F1/3203 ,  G06F1/3287 ,  G06F9/30181 ,  G06F9/3802 ,  G06F9/3869 ,  G06F9/5061 ,  G06F9/5094 ,  Y02D10/171 ,  Y02D10/22

Abstract: A method and apparatus for heterogeneous chip multiprocessors (CMP) via resource restriction. In one embodiment, the method includes the accessing of a resource utilization register to identify a resource utilization policy. Once accessed, a processor controller ensures that the processor core utilizes a shared resource in a manner specified by the resource utilization policy. In one embodiment, each processor core within a CMP includes an instruction issue throttle resource utilization register, an instruction fetch throttle resource utilization register and other like ways of restricting its utilization of shared resources within a minimum and maximum utilization level. In one embodiment, resource restriction provides a flexible manner for allocating current and power resources to processor cores of a CMP that can be controlled by hardware or software. Other embodiments are described and claimed.

Abstract translation: 一种通过资源限制的异构芯片多处理器（CMP）的方法和装置。 在一个实施例中，该方法包括访问资源利用寄存器以识别资源利用策略。 一旦被访问，处理器控制器确保处理器核心以资源利用策略指定的方式利用共享资源。 在一个实施例中，CMP中的每个处理器核心包括指令发布节流阀资源利用寄存器，指令提取节流阀资源利用寄存器以及在最小和最大利用水平内限制其对共享资源的利用的类似方式。 在一个实施例中，资源限制提供了将电流和功率资源分配给可由硬件或软件控制的CMP的处理器核心的灵活方式。 描述和要求保护其他实施例。

公开(公告)号：WO2013101840A1

公开(公告)日：2013-07-04

申请号：PCT/US2012/071668

申请日：2012-12-26

Applicant: INTEL CORPORATION ,  CHEE, Nicholas Cheng Hwa ,  FOSSUM, Tryggve ,  HASENPLAUGH, William C.

Inventor： CHEE, Nicholas Cheng Hwa ,  FOSSUM, Tryggve ,  HASENPLAUGH, William C.

IPC: G06F9/06 ,  G06F9/30

CPC classification number: G06F8/44 ,  G06F9/3001 ,  G06F9/30087 ,  G06F9/30174 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/462 ,  G06F11/0751

Abstract: Hardware compilation and/or translation with fault detection and roll back functionality are disclosed. Compilation and/or translation logic receives programs encoded in one language, and encodes the programs into a second language including instructions to support processor features not encoded into the original language encoding of the programs. In one embodiment, an execution unit executes instructions of the second language including an operation-check instruction to perform a first operation and record the first operation result for a comparison, and an operation-test instruction to perform a second operation and a fault detection operation by comparing the second operation result to the recorded first operation result. In some embodiments, an execution unit executes instructions of the second language including commit instructions to record execution checkpoint states of registers mapped to architectural registers, and roll-back instructions to restore the registers mapped to architectural registers to previously recorded execution checkpoint states.

Abstract translation: 公开了具有故障检测和回滚功能的硬件编译和/或翻译。 编译和/或翻译逻辑接收以一种语言编码的程序，并且将该程序编码成包括指令的第二语言，以支持未被编码为程序的原始语言编码的处理器特征。 在一个实施例中，执行单元执行包括执行第一操作的操作检查指令的第二语言的指令并记录用于比较的第一操作结果，以及执行第二操作和故障检测操作的操作测试指令 通过比较第二操作结果与记录的第一操作结果。 在一些实施例中，执行单元执行第二语言的指令，包括提交指令以记录映射到架构寄存器的寄存器的执行检查点状态，以及回滚指令，将映射到架构寄存器的寄存器恢复到先前记录的执行检查点状态。

公开(公告)号：WO2008124455A2

公开(公告)日：2008-10-16

申请号：PCT/US2008/059172

申请日：2008-04-02

Applicant: INTEL CORPORATION ,  ILLIKKAL, Ramesh Kumar ,  IYER, Ravishankar ,  MOSES, Jaideep ,  NEWELL, Don ,  FOSSUM, Tryggve

Inventor： ILLIKKAL, Ramesh Kumar ,  IYER, Ravishankar ,  MOSES, Jaideep ,  NEWELL, Don ,  FOSSUM, Tryggve

IPC: G06F1/26

CPC classification number: G06F9/5077 ,  G06F9/5094 ,  G06F2209/504 ,  Y02D10/22 ,  Y02D10/36

Abstract: A method and apparatus for throttling power and/or performance of processing elements based on a priority of software entities is herein described. Priority aware power management logic receives priority levels of software entities and modifies operating points of processing elements associated with the software entities accordingly. Therefore, in a power savings mode, processing elements executing low priority applications/tasks are reduced to a lower operating point, i.e. lower voltage, lower frequency, throttled instruction issue, throttled memory accesses, and/or less access to shared resources. In addition, utilization logic potentially trackes utilization of a resource per priority level, which allows the power manager to determine operating points based on the affect of each priority level on each other from the perspective of the resources themselves. Moreover, a software entity itself may assign operating points, which the power manager enforces.

Abstract translation: 这里描述了用于基于软件实体的优先级来节制处理元件的功率和/或性能的方法和设备。 优先级感知功率管理逻辑接收软件实体的优先级并相应地修改与软件实体相关联的处理元件的操作点。 因此，在省电模式下，执行低优先级应用/任务的处理元件被降低到较低的操作点，即较低电压，较低频率，节制指令问题，节制存储器访问和/或较少访问共享资源。 另外，利用率逻辑可能会跟踪每个优先级的资源利用率，这使得电源管理员可以从资源本身的角度出发，根据每个优先级对彼此的影响来确定操作点。 此外，软件实体本身可以分配电源管理器执行的操作点。