公开(公告)号：WO2009003120A1

公开(公告)日：2008-12-31

申请号：PCT/US2008/068395

申请日：2008-06-26

Applicant: QUALCOMM INCORPORATED ,  GE, Shaoping ,  CHAI, Chiaming ,  FISCHER, Jeffery Herbert

Inventor： GE, Shaoping ,  CHAI, Chiaming ,  FISCHER, Jeffery Herbert

IPC: H03K5/1534 ,  G01R29/027

CPC classification number: H03K5/1534 ,  H03K19/19

Abstract: A number of logic state catching circuits (200) are described which use a logic circuit (204) with a first input (210), a second input, (232) and an output. The logic circuit (204) is configured to respond to a change in state of a data value coupled to the first input (210) causing a representative value of the data „ value to be generated on the output(212). The second input (232) receives a latched version of the data value to hold the representative value on the output after the data value has returned to its original state. A latching element (206) is configured to respond to the change in state of the data value by latching the data value and to couple the latched version of the data value to the second input (232). A reset element (208) is configured to respond to a change in state of a clock input (230)by resetting the latching element. (206)

Abstract translation: 描述了使用具有第一输入（210），第二输入（232）和输出的逻辑电路（204）的多个逻辑状态捕捉电路（200）。 逻辑电路（204）被配置为响应耦合到第一输入（210）的数据值的状态变化，导致在输出（212）上产生数据“值的代表值”，第二输入 232）接收数据值的锁存版本，以在数据值已经返回到其原始状态之后将输出的代表值保持在该状态。锁存元件（206）被配置为通过锁存来响应数据值的状态改变 数据值并将锁存的数据值版本耦合到第二输入端（232），复位元件（208）被配置为通过复位锁存元件来响应时钟输入（230）的状态改变（ 206）