公开(公告)号：WO2013081596A1

公开(公告)日：2013-06-06

申请号：PCT/US2011/062585

申请日：2011-11-30

Applicant: INTEL CORPORATION ,  KANG, Xiaozhu ,  GEORGE, Biju ,  LUEH, Ken

Inventor： KANG, Xiaozhu ,  GEORGE, Biju ,  LUEH, Ken

IPC: G06F9/30 ,  G06F9/45

CPC classification number: G06F9/38 ,  G06F8/452 ,  G06F9/30 ,  G06F21/00

Abstract: Various embodiments are directed to a heterogeneous processor architecture comprised of a CPU and a GPU on the same processor die. The heterogeneous processor architecture may optimize source code in a GPU compiler using vector strip mining to reduce instructions of arbitrary vector lengths into GPU supported vector lengths and loop peeling. It may be first determined that the source code is eligible for optimization if more than one machine code instruction of compiled source code under-utilizes GPU instruction bandwidth limitations. The initial vector strip mining results may be discarded and the first iteration of the inner loop body may be peeled out of the loop. The type of operands in the source code may be lowered and the peeled out inner loop body of source code may be vector strip mined again to obtain optimized source code.

Abstract translation: 各种实施例涉及由同一处理器管芯上的CPU和GPU组成的异构处理器架构。 异构处理器架构可以使用向量带挖掘来优化GPU编译器中的源代码，以将任意矢量长度的指令减少到GPU支持的矢量长度和循环剥离。 如果编译源代码的多个机器码指令利用了GPU指令带宽限制，则可以首先确定源代码是否符合优化条件。 可以丢弃初始矢量条带挖掘结果，并且内环体的第一次迭代可能被剥离出环路。 可以降低源代码中的操作数类型，并且可以再次剥离源代码的剥离内圈体，以获得优化的源代码。