公开(公告)号：WO2018112340A1

公开(公告)日：2018-06-21

申请号：PCT/US2017/066670

申请日：2017-12-15

Applicant: OPTIMUM SEMICONDUCTOR TECHNOLOGIES, INC. ,  MOUDGILL, Mayan ,  HOANE, A., Joseph

Inventor： MOUDGILL, Mayan ,  HOANE, A., Joseph

IPC: G06F13/00

Abstract: A processor comprising a cache, the cache comprising a cache line, an execution unit to execute an atomic primitive to responsive to executing a read instruction to retrieve a data item from a memory location, cause to store a copy of the data item in the cache line, execute a lock instruction to lock the cache line to the processor, execute at least one instruction while the cache line is locked to the processor, and execute an unlock instruction to cause the cache controller to release the cache line from the processor.