公开(公告)号：WO2020190429A1

公开(公告)日：2020-09-24

申请号：PCT/US2020/017897

申请日：2020-02-12

Applicant: INTEL CORPORATION ,  VEMULAPALLI, Vikranth ,  STRIRAMASSARMA, Lakshminarayanan ,  MACPHERSON, Mike ,  ANANTARAMAN, Aravindh ,  ASHBAUGH, Ben ,  RAMADOSS, Murali ,  SADLER, William B. ,  PEARCE, Jonathan ,  JANUS, Scott ,  INSKO, Brent ,  RANGANATHAN, Vasanth ,  SINHA, Kamal ,  HUNTER, Arthur ,  SURTI, Prasoonkumar ,  GALOPPO VON BORRIES, Nicolas ,  RAY, Joydeep ,  APPU, Abhisek R. ,  OULD-AHMED-VALL, ElMoustapha ,  KOKER, Altug ,  KIM, Sungye ,  MAIYURAN, Subramaniam ,  ANDREI, Valentin

Inventor： VEMULAPALLI, Vikranth ,  STRIRAMASSARMA, Lakshminarayanan ,  MACPHERSON, Mike ,  ANANTARAMAN, Aravindh ,  ASHBAUGH, Ben ,  RAMADOSS, Murali ,  SADLER, William B. ,  PEARCE, Jonathan ,  JANUS, Scott ,  INSKO, Brent ,  RANGANATHAN, Vasanth ,  SINHA, Kamal ,  HUNTER, Arthur ,  SURTI, Prasoonkumar ,  GALOPPO VON BORRIES, Nicolas ,  RAY, Joydeep ,  APPU, Abhisek R. ,  OULD-AHMED-VALL, ElMoustapha ,  KOKER, Altug ,  KIM, Sungye ,  MAIYURAN, Subramaniam ,  ANDREI, Valentin

IPC: G06F12/0862 ,  G06F12/0897 ,  G06F12/0888 ,  G06F9/38

Abstract: Embodiments are generally directed to data prefetching for graphics data processing. An embodiment of an apparatus includes one or more processors including one or more graphics processing units (GPUs); and a plurality of caches to provide storage for the one or more GPUs, the plurality of caches including at least an L1 cache and an L3 cache, wherein the apparatus to provide intelligent prefetching of data by a prefetcher of a first GPU of the one or more GPUs including measuring a hit rate for the L1 cache; upon determining that the hit rate for the L1 cache is equal to or greater than a threshold value, limiting a prefetch of data to storage in the L3 cache, and upon determining that the hit rate for the L1 cache is less than a threshold value, allowing the prefetch of data to the L1 cache.

公开(公告)号：WO2020190432A1

公开(公告)日：2020-09-24

申请号：PCT/US2020/017996

申请日：2020-02-12

Applicant: INTEL CORPORATION ,  SURTI, Prasoonkumar ,  HUNTER, Arthur ,  SINHA, Kamal ,  JANUS, Scott ,  INSKO, Brent ,  RANGANATHAN, Vasanth ,  STRIRAMASSARMA, Lakshminarayanan

Inventor： SURTI, Prasoonkumar ,  HUNTER, Arthur ,  SINHA, Kamal ,  JANUS, Scott ,  INSKO, Brent ,  RANGANATHAN, Vasanth ,  STRIRAMASSARMA, Lakshminarayanan

IPC: G06T15/00

Abstract: Embodiments are generally directed to multi-tile graphics processor rendering. An embodiment of an apparatus includes a memory for storage of data; and one or more processors including a graphics processing unit (GPU) to process data, wherein the GPU includes a plurality of GPU tiles, wherein, upon geometric data being assigned to each of a plurality of screen tiles, the apparatus is to transfer the geometric data to the plurality of GPU tiles.