公开(公告)号：WO2005013599A3

公开(公告)日：2005-12-29

申请号：PCT/US2004024496

申请日：2004-07-29

Applicant: CROSSROADS SYS INC ,  VILA DIEGO F ,  MATEUS MARCUS S

Inventor： VILA DIEGO F ,  MATEUS MARCUS S

IPC: H04L7/04 ,  H04J3/06

CPC classification number: H04L7/043 ,  H04L2007/045

Abstract: Systems and methods for synchronizing digital communications links (Fig 2B), wherein one embodiment implemented in a receiver of a communications link comprises a shift register coupled to a transmission medium to receive synchronization data and a feedback circuit coupled to the shift register, wherein one or more cells of the shift register are configured to alternatively accept as input either a bit from a preceding cell or a received bit of synchronization data. The first occurs prior to synchronization, while the second occurs after synchronization. A counter is used to assert a signal indicating that the transmitter and receiver are synchronized.

Abstract translation: 用于同步数字通信链路的系统和方法（图2B），其中在通信链路的接收机中实现的一个实施例包括耦合到传输介质以接收同步数据的移位寄存器和耦合到移位寄存器的反馈电路，其中一个或 移位寄存器的更多单元被配置为交替地接受来自前一个单元的位或者接收的同步数据位的输入。 第一个发生在同步之前，而第二个发生在同步之后。 计数器用于断言指示发送器和接收器同步的信号。

公开(公告)号：WO2005013599A2

公开(公告)日：2005-02-10

申请号：PCT/US2004/024496

申请日：2004-07-29

Applicant: CROSSROADS SYSTEMS, INC. ,  VILA, Diego, F. ,  MATEUS, Marcus, S.

Inventor： VILA, Diego, F. ,  MATEUS, Marcus, S.

IPC: H04N

CPC classification number: H04L7/043 ,  H04L2007/045

Abstract: Systems and methods for synchronizing digital communications links, wherein one embodiment implemented in a receiver of a communications link comprises a shift register coupled to a transmission medium to receive synchronization data and a feedback circuit coupled to the shift register, wherein one or more cells of the shift register are configured to alternatively accept as input either a bit from a preceding cell or a received bit of synchronization data. The first occurs prior to synchronization, while the second occurs after synchronization. A counter is used to assert a signal indicating that the transmitter and receiver are synchronized.

Abstract translation: 用于同步数字通信链路的系统和方法，其中在通信链路的接收机中实现的一个实施例包括耦合到传输介质以接收同步数据的移位寄存器和耦合到移位寄存器的反馈电路，其中， 移位寄存器被配置为交替地接受来自前一个单元的位或者同步数据的接收位的输入。 第一个发生在同步之前，而第二个发生在同步之后。 计数器用于断言指示发送器和接收器同步的信号。