公开(公告)号：WO2008083856A1

公开(公告)日：2008-07-17

申请号：PCT/EP2007/050268

申请日：2007-01-11

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  KELLEHER, Paul ,  GAYER, Patrick ,  MCSWINEY, Diarmuid

Inventor： KELLEHER, Paul ,  GAYER, Patrick ,  MCSWINEY, Diarmuid

IPC: H04B1/16

CPC classification number: H04W52/0241 ,  H04J3/0697 ,  H04L7/042 ,  H04W88/06 ,  Y02D70/122 ,  Y02D70/124 ,  Y02D70/144

Abstract: A communication device (300) is capable of supporting communication compliant with a Dual- Mode 2.5G and 3G interface baseband (BB)-radio frequency (RF) interface standard and comprises a data interface (305) operably coupled to a number sub-systems (310, 120) and a clock circuit generating a plurality of clock phases for supporting communication there between. At least one of the number of sub-systems (310, 320) comprises a line driver and a line receiver (430); wherein the communication device (300) is characterised in that the line receiver (430) determines an end of a received data frame sent across the data interface (305) and in response thereto switches itself off.

Abstract translation: 通信设备（300）能够支持符合双模2.5G和3G接口基带（BB） - 射频（RF）接口标准的通信，并且包括数据接口（305），其可操作地耦合到多个子系统 （310,120）和产生多个时钟相位的时钟电路，用于支持其间的通信。 多个子系统（310,320）中的至少一个包括线路驱动器和线路接收器（430）; 其特征在于，所述通信设备（300）的特征在于，所述线路接收器（430）确定通过所述数据接口（305）发送的接收数据帧的结束，并响应于此自身断开。

公开(公告)号：WO2008100686A1

公开(公告)日：2008-08-21

申请号：PCT/US2008/051838

申请日：2008-01-24

Applicant: FREESCALE SEMICONDUCTOR INC. ,  LUCE, Lawrence B. ,  KELLEHER, Paul ,  MCSWINEY, Diarmuid

Inventor： LUCE, Lawrence B. ,  KELLEHER, Paul ,  MCSWINEY, Diarmuid

IPC: H04B1/38 ,  H04B1/48

CPC classification number: G01R31/31716

Abstract: A digital interface (22) includes a self-test structure (56). The structure (56) includes a transmit section (52) and a receive section (36) having a correlator (68). A method (114) of testing the interface (22) entails coupling the receive section (36) with the transmit section (52) and communicating a test data structure (86) from the transmit section (52) to the receive section (36) at a high data rate. The test data structure (86) includes a pre-defined sync pattern (88), a header (90), and a payload (92). The receive section (36) detects the sync pattern (88) and performs time frame synchronization (148) at the correlator (68). When synchronization (148) is successful, the receive section (36) decodes (154, 162) the header (90) and the payload (92). If time frame synchronization (148) and decoding (154, 162) are successful, a validation indicator (100) is output for external observation at a low data rate.

Abstract translation: 数字接口（22）包括自检结构（56）。 结构（56）包括具有相关器（68）的发射部分（52）和接收部分（36）。 测试接口（22）的方法（114）需要将接收部分（36）与发送部分（52）耦合并将测试数据结构（86）从发送部分（52）传送到接收部分（36） 以高数据速率。 测试数据结构（86）包括预定义同步模式（88），报头（90）和有效载荷（92）。 接收部分（36）检测同步模式（88）并在相关器（68）处执行时间帧同步（148）。 当同步（148）成功时，接收部分（36）解码（154,162）标题（90）和有效载荷（92）。 如果时间帧同步（148）和解码（154,162）成功，则以低数据速率输出验证指示符（100）以进行外部观察。

公开(公告)号：WO2008083850A1

公开(公告)日：2008-07-17

申请号：PCT/EP2007/050188

申请日：2007-01-09

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  KELLEHER, Paul ,  MCSWINEY, Diarmuid ,  O'KEEFFE, Conor

Inventor： KELLEHER, Paul ,  MCSWINEY, Diarmuid ,  O'KEEFFE, Conor

IPC: H04L7/04

CPC classification number: H04L7/042 ,  H04B1/005 ,  H04B1/70753 ,  H04L7/0337

Abstract: An electronic device (100) comprises a number of sub-systems (110, 120) coupled via an interface. One of the number of sub-systems (110, 120) comprises logic for receiving a frame of input data having a plurality of phases on respective data paths. The electronic device (100) further comprises logic for performing cross correlation on the received input data with a pre-determined bit pattern (510), operably coupled to selection logic, for selecting a single phase from the plurality of phases sent to the interface to sample the received input data in a middle region of a data bit period in response to the cross correlation.

Abstract translation: 电子设备（100）包括通过接口耦合的多个子系统（110,120）。 多个子系统（110,120）中的一个包括用于接收在相应数据路径上具有多个相位的输入数据的帧的逻辑。 电子设备（100）还包括用于以可选择地耦合到选择逻辑的预定位模式（510）对所接收的输入数据执行互相关的逻辑，用于从发送到接口的多个阶段中选择单个相位 响应于互相关，在数据比特周期的中间区域中对接收到的输入数据进行采样。

公开(公告)号：WO2008083849A1

公开(公告)日：2008-07-17

申请号：PCT/EP2007/050186

申请日：2007-01-09

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  KELLEHER, Paul ,  MCSWINEY, Diarmuid ,  O'KEEFFE, Conor ,  QUIROGA, Emilio ,  SONI, Samir

Inventor： KELLEHER, Paul ,  MCSWINEY, Diarmuid ,  O'KEEFFE, Conor ,  QUIROGA, Emilio ,  SONI, Samir

IPC: H04L7/033

CPC classification number: H04L7/0338 ,  H04L7/042

Abstract: A wireless communication device (100) comprises a number of sub-systems (110, 120) and clock generation logic arranged to generate at least one clock signal to be applied to the number of subsystems (110, 120). One of the number of sub-systems (110, 120) comprises sampling logic for receiving input data and performing initial sampling on an input data bit using multiple separated phases of a clock period of the at least one clock signal applied to the sampling logic thereby producing multiple phase separated sampled outputs of the input data bit. The sampling logic is configured to perform a number of re-sampling operations on the multiple phase separated sampled outputs at a number of intermediate phases thereby producing multiple phase separated intermediate sampled outputs prior to performing a final sample of the multiple phase separated intermediate sampled outputs at a single phase of the at least one clock signal to produce a sampled input data signal.

Abstract translation: 无线通信设备（100）包括多个子系统（110,120）和时钟生成逻辑，时钟生成逻辑被配置为产生要施加到子系统（110,120）的数量的至少一个时钟信号。 多个子系统（110,120）中的一个包括用于接收输入数据的采样逻辑，并且使用应用于采样逻辑的至少一个时钟信号的时钟周期的多个分离相位对输入数据位执行初始采样， 产生输入数据位的多相分离采样输出。 采样逻辑被配置为在多个中间相位的多相分离采样输出上执行多个重采样操作，从而在执行多相分离的中间采样输出的最终采样之前产生多相分离中间采样输出 所述至少一个时钟信号的单相以产生采样的输入数据信号。