公开(公告)号：WO2008048940A3

公开(公告)日：2008-04-24

申请号：PCT/US2007/081428

申请日：2007-10-15

Applicant: QUALCOMM INCORPORATED ,  JIAO, Guofang ,  RUTTENBERG, Brain ,  YU, Chun ,  DU, Yun

Inventor： JIAO, Guofang ,  RUTTENBERG, Brain ,  YU, Chun ,  DU, Yun

IPC: G06T15/00

Abstract: This disclosure describes a graphics processing unit (GPU) pipeline that uses one or more shared arithmetic logic units (ALUs). In order to facilitate such sharing of ALUs, the stages of the disclosed GPU pipeline may be rearranged relative to conventional GPU pipelines. In addition, by rearranging the stages of the GPU pipeline, efficiencies may be achieved in the image processing. Unlike conventional GPU pipelines, for example, an attribute gradient setup stage can be located much later in the pipeline, and the attribute interpolator stage may immediately follow the attribute gradient setup stage. This allows sharing of an ALU by the attribute gradient setup and attribute interpolator stages. Several other techniques and features for the GPU pipeline are also described, which may improve performance and possibly achieve additional processing efficiencies.

公开(公告)号：WO2008048940A2

公开(公告)日：2008-04-24

申请号：PCT/US2007081428

申请日：2007-10-15

Applicant: QUALCOMM INC ,  JIAO GUOFANG ,  RUTTENBERG BRAIN ,  YU CHUN ,  DU YUN

Inventor： JIAO GUOFANG ,  RUTTENBERG BRAIN ,  YU CHUN ,  DU YUN

IPC: G06T15/00

CPC classification number: G06T15/005

Abstract: This disclosure describes a graphics processing unit (GPU) pipeline that uses one or more shared arithmetic logic units (ALUs). In order to facilitate such sharing of ALUs, the stages of the disclosed GPU pipeline may be rearranged relative to conventional GPU pipelines. In addition, by rearranging the stages of the GPU pipeline, efficiencies may be achieved in the image processing. Unlike conventional GPU pipelines, for example, an attribute gradient setup stage can be located much later in the pipeline, and the attribute interpolator stage may immediately follow the attribute gradient setup stage. This allows sharing of an ALU by the attribute gradient setup and attribute interpolator stages. Several other techniques and features for the GPU pipeline are also described, which may improve performance and possibly achieve additional processing efficiencies.

Abstract translation: 本公开描述了使用一个或多个共享算术逻辑单元（ALU）的图形处理单元（GPU）流水线。 为了促进ALU的这种共享，所公开的GPU流水线的阶段可以相对于传统的GPU管线重新排列。 此外，通过重新排列GPU流水线的各个阶段，可以在图像处理中实现效率。 与传统GPU流水线不同，例如，属性梯度建立阶段可以在流水线后面定位，并且属性内插器阶段可以立即跟随属性梯度建立阶段。 这允许通过属性渐变设置和属性内插器阶段共享ALU。 还描述了用于GPU流水线的若干其它技术和特征，其可以提高性能并且可能实现额外的处理效率。