公开(公告)号：WO2008074158A1

公开(公告)日：2008-06-26

申请号：PCT/CA2007/002352

申请日：2007-12-21

Applicant: SIRIFIC WIRELESS CORPORATION ,  BELLAOUAR, Abdellatif ,  MANKU, Tajinder

Inventor： BELLAOUAR, Abdellatif ,  MANKU, Tajinder

IPC: H04B1/40 ,  H04B7/005

CPC classification number: H03G3/3047 ,  H04B2001/0416

Abstract: A closed loop power output calibration system for variable power output wireless devices. The wireless device includes a wireless transceiver having a transmit core coupled to a discrete power amplifier. Power detection circuitry formed in the wireless transceiver provides a detected power level of the power amplifier, and a reference power level, both of which are converted to digital signals using existing I and Q signal analog to digital converters in the receiver core. The digital signals are processed to cancel power distortion and temperature effects to provide a resulting power feedback signal. Corrective control signals are generated in response to the power feedback signal relative to a desired power output level. The gain in the transmit core is then adjusted in response to the corrective control signals such that the power amplifier outputs the target output power level.

Abstract translation:

用于可变功率输出无线设备的闭环功率输出校准系统。 无线设备包括具有耦合到分立功率放大器的发射核心的无线收发器。 在无线收发器中形成的功率检测电路提供功率放大器的检测功率电平和参考功率电平，二者均使用接收器核心中现有的I和Q信号模数转换器转换为数字信号。 对数字信号进行处理以消除功率失真和温度效应，以提供最终的功率反馈信号。 响应于功率反馈信号相对于期望的功率输出水平而生成校正控制信号。 然后响应于校正控制信号调整发送核心中的增益，使得功率放大器输出目标输出功率电平。

公开(公告)号：WO2007065264A1

公开(公告)日：2007-06-14

申请号：PCT/CA2006/001995

申请日：2006-12-08

Applicant: SIRIFIC WIRELESS CORPORATION ,  BELLAOUAR, Abdellatif

Inventor： BELLAOUAR, Abdellatif

IPC: H01L45/00 ,  H03B5/08

CPC classification number: H03J3/20 ,  H03B5/1243 ,  H03B2201/025 ,  H03J2200/10

Abstract: A method of selecting fabrication parameters for an on-chip inductor of an integrated circuit. The integrated circuit includes a capacitor fabricated prior to the inductor. The capacitance of the capacitor is measured and, based on the measured capacitance and on a desired frequency range, a suitable inductor is fabricated. The integrated circuit may include a voltage controlled oscillator (VCO), and the selection of the fabrication parameters of the inductor includes the selection of a lithography mask for the fabrication of the inductor for maximizing yield across the wafer. Therefore, the integrated circuit can have exactly one VCO for covering the desired frequency range, as opposed to at least two VCO's with overlapping frequency ranges, thereby saving significant silicon area and increasing the yield per wafer.

Abstract translation: 选择集成电路的片上电感器的制造参数的方法。 集成电路包括在电感器之前制造的电容器。 测量电容器的电容，并根据测得的电容和所需的频率范围，制造合适的电感器。 集成电路可以包括压控振荡器（VCO），并且电感器的制造参数的选择包括选择用于制造电感器的光刻掩模，以最大限度地提高晶片的产量。 因此，与具有重叠频率范围的至少两个VCO相反，集成电路可以具有恰好一个用于覆盖期望频率范围的VCO，从而节省显着的硅面积并提高每个晶片的产量。

公开(公告)号：WO2003071673A3

公开(公告)日：2003-08-28

申请号：PCT/CA2003/000257

申请日：2003-02-25

Applicant: SIRIFIC WIRELESS CORPORATION ,  MANKU, Tajinder

Inventor： MANKU, Tajinder

IPC: H03D7/16

Abstract: There is a need for an inexpensive, high-performance, fully-integrable, multi­standard transceiver, which suppresses spurious noise signals. The invention provides a topology that satisfies this need, providing a first mixer for receiving an input signal x(t), and mixing it with a multi-tonal mixing signal φ1 to generate an output signal φ1 x(t), and providing a second mixer for receiving the φ1 x(t) signal, and mixing it with a mono-tonal mixing signal φ2, to generate an output signal φ1 φ2 x(t). The two mixing signals emulate an LO signal because φ1 * φ2 has significant power at the frequency of the LO signal being emulated. The topology also includes a power measurement circuit for measuring the power of the output signal φ1 φ2 x(t). This power output signal is used to vary the characteristics of the mono-tonal mixing signal φ2 to reduce the power level of said output signal.

公开(公告)号：WO2008089574A1

公开(公告)日：2008-07-31

申请号：PCT/CA2008/000162

申请日：2008-01-25

Applicant: SIRIFIC WIRELESS CORPORATION ,  MANKU, Tajinder ,  BELLAOUAR, Abdellatif ,  HOLDEN, Alan, R. ,  SAFIRI, Hamid, R.

Inventor： MANKU, Tajinder ,  BELLAOUAR, Abdellatif ,  HOLDEN, Alan, R. ,  SAFIRI, Hamid, R.

IPC: H04B1/26 ,  H04B17/00 ,  H04Q7/32

CPC classification number: H04B1/12 ,  H03D2200/0045 ,  H04B17/21

Abstract: An integrated automatic IIP2 calibration architecture for wireless transceivers is disclosed. The architecture enables a wireless transceiver to generate a test radio frequency (RF) signal having a second order tone with minimal additional circuitry. In particular, the test RF signal is generated using a combination of native transceiver circuits and test adaptor circuits. Native transceiver circuits are those circuits implemented on the transceiver chip for executing native transceiver functions during normal operation, which can be used for generating the test (RF) signal. Test adaptor circuits are added to the transceiver chip, more specifically to the native circuits, for enabling the native circuits to generate the test RF signal in a self-test mode of operation. Circuits for implementing a particular IIP2 minimizing scheme can be included on the transceiver chip for automatic IIP2 calibration during the self-test mode of operation.

Abstract translation: 公开了一种用于无线收发器的集成自动IIP2校准架构。 该架构使得无线收发器能够产生具有最小附加电路的具有二阶音调的测试射频（RF）信号。 特别地，使用本机收发器电路和测试适配器电路的组合产生测试RF信号。 本地收发器电路是在收发器芯片上实现的用于在正常操作期间执行本机收发器功能的那些电路，其可用于产生测试（RF）信号。 测试适配器电路被添加到收发器芯片中，更具体地被添加到本地电路，用于使得本机电路能够以自测试操作模式生成测试RF信号。 在自检操作模式下，用于实现特定IIP2最小化方案的电路可以包括在收发器芯片上用于自动IIP2校准。

公开(公告)号：WO2008074149A1

公开(公告)日：2008-06-26

申请号：PCT/CA2007/002329

申请日：2007-12-20

Applicant: SIRIFIC WIRELESS CORPORATION ,  EMBABI, Sherif, H., K. ,  BELLAOUAR, Abdellatif ,  FRECHETTE, Michel, J., G., J., P.

Inventor： EMBABI, Sherif, H., K. ,  BELLAOUAR, Abdellatif ,  FRECHETTE, Michel, J., G., J., P.

IPC: H04B1/04 ,  H04B7/005

CPC classification number: H03G3/3042 ,  H03G1/04

Abstract: An adaptive current control circuit for reduced power consumption and minimized gain shift in a variable gain amplifier. An automatic gain control circuit provides gain control voltages in response to a gain control signal. The gain control voltages are used by the variable gain amplifier to set the gain of the output signal for wireless transmit operations. The adaptive current control circuit receives the same gain control voltages for reducing current to the variable gain amplifier during low gain operation, while providing higher currents during high gain operation. The current that is provided is a hybrid mix of proportional to absolute temperature (PTAT) current and complementary to absolute temperature (CTAT) current for minimizing temperature effects on the gain. The ratio of PTAT current and CTAT current is adjustable for specific temperature ranges to further minimize temperature effects on the gain.

Abstract translation: 一种自适应电流控制电路，用于降低可变增益放大器的功耗和最小化增益偏移。 自动增益控制电路响应增益控制信号提供增益控制电压。 可变增益放大器使用增益控制电压来设置无线发射操作的输出信号的增益。 自适应电流控制电路在低增益操作期间接收相同的增益控制电压，以减小电流到可变增益放大器，同时在高增益操作期间提供更高的电流。 提供的电流是与绝对温度（PTAT）电流成比例和与绝对温度（CTAT）电流互补的混合混合，以最小化对增益的温度影响。 PTAT电流和CTAT电流的比例可针对特定温度范围进行调节，以进一步降低温度对增益的影响。

公开(公告)号：WO2007068089A1

公开(公告)日：2007-06-21

申请号：PCT/CA2006/001986

申请日：2006-12-06

Applicant: SIRIFIC WIRELESS CORPORATION ,  EMBABI, Sherif, H. K. ,  HOLDEN, Alan, R. ,  JAEHNIG, Jason, P. ,  BELLAOUAR, Abdellatif

Inventor： EMBABI, Sherif, H. K. ,  HOLDEN, Alan, R. ,  JAEHNIG, Jason, P. ,  BELLAOUAR, Abdellatif

IPC: H03D7/18 ,  H03D7/14 ,  H04B1/12 ,  H04B1/30

CPC classification number: H03D7/1441 ,  H03D7/1433 ,  H03D7/1458 ,  H03D7/1466 ,  H03D2200/0047 ,  H03D2200/0088

Abstract: A passive CMOS differential mixer circuit with a mismatch correction circuit for balancing the electrical characteristics of the two output paths. Once the output paths of the differential circuit are balanced, or matched as closely as possible, second order intermodulation product generation can be inhibited or at least reduced to acceptable levels. The mismatch correction circuit receives a digital offset signal, and generates one or more voltage signals to be selectively applied to the signal paths of the passive differential mixer circuit. The voltage signals can be adjusted back gate bias voltages applied to the bulk terminals of selected transistors to adjust their threshold voltages, or the voltage signals can be adjusted common mode voltages applied directly to a selected signal path. Since the differential mixer circuit is passive, no DC current contribution to noise is generated. The switching transistors of the mixer circuit can be maintained at minimal dimensions to reduce switching signal drive loading, resulting in lower power consumption and higher operating frequencies than if larger switching transistors were used

Abstract translation: 一种具有用于平衡两个输出路径的电气特性的失配校正电路的无源CMOS差分混频器电路。 一旦差分电路的输出路径平衡或尽可能匹配，可以抑制二阶互调乘积的产生或至少降低到可接受的水平。 失配校正电路接收数字偏移信号，并产生一个或多个电压信号以选择性地施加到无源差分混频器电路的信号路径。 电压信号可以调节施加到所选晶体管的体积端子的反向栅极偏置电压以调整其阈值电压，或者可以将电压信号调整为直接施加到选定信号路径的共模电压。 由于差分混频器电路是无源的，所以不产生直流电流对噪声的贡献。 混合电路的开关晶体管可以保持在最小的尺寸以减少开关信号驱动负载，导致比使用更大的开关晶体管时更低的功耗和更高的工作频率

公开(公告)号：WO2005109628A1

公开(公告)日：2005-11-17

申请号：PCT/CA2005/000798

申请日：2005-05-12

Applicant: SIRIFIC WIRELESS CORPORATION ,  MANKU, Tajinder

Inventor： MANKU, Tajinder

IPC: H03F1/32

CPC classification number: H03K5/1252 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1491 ,  H03F1/3211 ,  H03F1/3223 ,  H03F3/24 ,  H03F3/45183 ,  H03F2200/372 ,  H03F2200/87 ,  H03F2203/45318 ,  H03F2203/45366 ,  H03F2203/45498 ,  H03F2203/45544 ,  H03K5/02 ,  H04B1/0475 ,  H04B1/123 ,  H04B2001/0441

Abstract: A CMOS transconductor for cancelling third-order intermodulation is provided. The transconductor includes a transconductance circuit and a tuneable distortion circuit. The transconductance circuit takes an input voltage and generates an output current having a transconductance element and an IM3 element. The distortion circuit takes the same input voltage and generates a current having an IM3 element of equal amplitude and opposite phase to the IM3 element of the transconductance circuit. A controller circuit tunes the distortion circuit to adjust its IM3 element to substantially equal the amplitude of the IM3 of the transconductance circuit. The distortion and transconductance circuits are arranged to sum their output currents thereby effectively cancelling the IM3 elements, leaving the transconductance relatively unmodified.

Abstract translation: 提供了用于消除三阶互调的CMOS跨导体。 跨导体包括跨导电路和可调谐失真电路。 跨导电路采用输入电压并产生具有跨导元件和IM3元件的输出电流。 失真电路采用相同的输入电压，并产生具有与跨导电路的IM3元件相等幅度和相反相位的IM3元件的电流。 控制器电路调谐失真电路以将其IM3元件调整为基本上等于跨导电路的IM3的幅度。 失真和跨导电路被布置为对其输出电流求和，从而有效地消除IM3元件，从而使跨导相对未修改。

公开(公告)号：WO2003071673A2

公开(公告)日：2003-08-28

申请号：PCT/CA2003/000257

申请日：2003-02-25

Applicant: SIRIFIC WIRELESS CORPORATION ,  MANKU, Tajinder

Inventor： MANKU, Tajinder

IPC: H03D

CPC classification number: H03D7/16

Abstract: There is a need for an inexpensive, high-performance, fully-integrable, multi­standard transceiver, which suppresses spurious noise signals. The invention provides a topology that satisfies this need, providing a first mixer for receiving an input signal x(t), and mixing it with a multi-tonal mixing signal φ1 to generate an output signal φ1 x(t), and providing a second mixer for receiving the φ1 x(t) signal, and mixing it with a mono-tonal mixing signal φ2, to generate an output signal φ1 φ2 x(t). The two mixing signals emulate an LO signal because φ1 * φ2 has significant power at the frequency of the LO signal being emulated. The topology also includes a power measurement circuit for measuring the power of the output signal φ1 φ2 x(t). This power output signal is used to vary the characteristics of the mono-tonal mixing signal φ2 to reduce the power level of said output signal.

Abstract translation: 需要一种廉价，高性能，完全可集成的多标准收发器，可以抑制杂散噪声信号。 本发明提供了一种满足这种需求的拓扑结构，提供了一个用于接收输入信号xt的第一混频器，并将其与多音调混合信号phi1进行混频以产生输出信号phi1 xt，并提供一个第二混频器，用于接收第一个 信号，并将其与单声道混合信号phi2混合，以产生输出信号phi1 phi2 xt。 两个混频信号模拟一个LO信号，因为在正在仿真的LO信号的频率上，phi1 ast phi2具有显着的功率。 拓扑结构还包括用于测量输出信号phi1 phi2 xt的功率的功率测量电路。 该功率输出信号用于改变单声道混合信号phi2的特性，以降低所述输出信号的功率电平。

公开(公告)号：WO2008134884A1

公开(公告)日：2008-11-13

申请号：PCT/CA2008/000856

申请日：2008-05-05

Applicant: SIRIFIC WIRELESS CORPORATION ,  DEVISON, Stephen, Arnold

Inventor： DEVISON, Stephen, Arnold

IPC: H04B1/40 ,  H04B7/005 ,  H04B7/26 ,  H04Q7/32

CPC classification number: H04B1/40

Abstract: Peripheral components of a wireless radio system can be controlled by a wireless transceiver. The transceiver stores parallel or serial bit patterns in memory, each bit pattern corresponding to a particular control configuration for one or more peripheral components. A further control device, such as baseband controller, issues an address corresponding to the desired functional operation of the peripheral components to the transceiver. A memory sub-system of the transceiver uses the address to output the appropriate bit pattern. The bit pattern can be provided in parallel to statically control individual control lines, or can be converted into a serial bitstream decodable by a command decoder. The command decoder can then decode the bitstream and locally issue the appropriate control signals for the peripheral components.

Abstract translation: 无线无线电系统的外围组件可以由无线收发器控制。 收发器将并行或串行位模式存储在存储器中，每个位模式对应于一个或多个外围组件的特定控制配置。 诸如基带控制器的另外的控制装置向收发器发出与周边组件的所需功能操作相对应的地址。 收发器的存储器子系统使用地址输出适当的位模式。 可以并行提供位模式以静态控制单独的控制线，或者可以将其转换为由命令解码器解码的串行比特流。 命令解码器然后可以对比特流进行解码，并且在本地发出适用于外围组件的控制信号。

公开(公告)号：WO2008074147A1

公开(公告)日：2008-06-26

申请号：PCT/CA2007/002318

申请日：2007-12-20

Applicant: SIRIFIC WIRELESS CORPORATION ,  HOLDEN, Alan, R. ,  SAFIRI, Hamid, R. ,  FRECHETTE, Michel, J., G., J., P. ,  EMBABI, Sherif, H., K. ,  BELLAOUAR, Abdellatif ,  DEVISON, Stephen, Arnold ,  MANKU, Tajinder

Inventor： HOLDEN, Alan, R. ,  SAFIRI, Hamid, R. ,  FRECHETTE, Michel, J., G., J., P. ,  EMBABI, Sherif, H., K. ,  BELLAOUAR, Abdellatif ,  DEVISON, Stephen, Arnold ,  MANKU, Tajinder

IPC: H04B1/04 ,  H04Q7/32

CPC classification number: H03G3/3047

Abstract: A power ramping circuit for use in the transmit path of a radio frequency (RF) circuit. The power ramping circuit includes parallel connected transistors used as logarithmic resistor attenuators for adjusting current to a mixer circuit in the transmit path. The parallel connected transistors can be sized differently, and are sequentially turned off to gradually increase the current provided to the mixer circuit. A ramp control circuit controls the parallel connected transistors in response to either an analog signal or a digital signal.

Abstract translation: 一种用于射频（RF）电路的发射路径的功率斜坡电路。 功率斜坡电路包括并联的晶体管，用作对数电阻衰减器，用于调节到发射路径中的混频器电路的电流。 并联连接的晶体管的尺寸可以不同，并被依次关闭，以逐渐增加提供给混频器电路的电流。 斜坡控制电路响应于模拟信号或数字信号来控制并联的晶体管。