公开(公告)号：WO2010017077A3

公开(公告)日：2010-02-11

申请号：PCT/US2009/052118

申请日：2009-07-29

Applicant: QUALCOMM INCORPORATED ,  STREETT, Daren, Eugene ,  STEMPEL, Brian, Michael

Inventor： STREETT, Daren, Eugene ,  STEMPEL, Brian, Michael

IPC: G06F9/38 ,  G06F12/08 ,  G06F9/48

Abstract: Techniques for interrupt processing are described. An exceptional condition is detected in one or more stages of an instruction pipeline in a processor. In response to the detected exceptional condition and prior to the processor accepting an interrupt in response to the detected exceptional condition, an instruction cache is checked for the presence of an instruction at a starting address of an interrupt handler. The instruction at the starting address of the interrupt vector table is prefetched from storage above the instruction cache when the instruction is not present in the instruction cache to load the instruction in the instruction cache, whereby the instruction is made available in the instruction cache by the time the processor accepts the interrupt in response to the detected exceptional condition.

公开(公告)号：WO2010017077A2

公开(公告)日：2010-02-11

申请号：PCT/US2009052118

申请日：2009-07-29

Applicant: QUALCOMM INC ,  STREETT DAREN EUGENE ,  STEMPEL BRIAN MICHAEL

Inventor： STREETT DAREN EUGENE ,  STEMPEL BRIAN MICHAEL

IPC: G06F9/38 ,  G06F9/48 ,  G06F12/08

CPC classification number: G06F12/0897 ,  G06F9/3802 ,  G06F9/3865 ,  G06F9/3867 ,  G06F9/4812 ,  G06F12/0862

Abstract: Techniques for interrupt processing are described. An exceptional condition is detected in one or more stages of an instruction pipeline in a processor. In response to the detected exceptional condition and prior to the processor accepting an interrupt in response to the detected exceptional condition, an instruction cache is checked for the presence of an instruction at a starting address of an interrupt handler. The instruction at the starting address of the interrupt vector table is prefetched from storage above the instruction cache when the instruction is not present in the instruction cache to load the instruction in the instruction cache, whereby the instruction is made available in the instruction cache by the time the processor accepts the interrupt in response to the detected exceptional condition.

Abstract translation: 描述中断处理技术。 在处理器中的指令流水线的一个或多个阶段中检测到异常情况。 响应于检测到的异常情况，并且在处理器响应于检测到的异常情况接受中断之前，检查指令高速缓存在中断处理程序的起始地址处是否存在指令。 当指令不存在于指令高速缓存中以将指令加载到指令高速缓存中时，中断向量表的起始地址处的指令从指令高速缓存上的存储器中预取，由此指令在指令高速缓存中可用 处理器响应于检测到的异常情况接受中断的时间。

公开(公告)号：WO2007124307A3

公开(公告)日：2007-12-27

申请号：PCT/US2007066802

申请日：2007-04-17

Applicant: QUALCOMM INC ,  SARTORIUS THOMAS ANDREW ,  SMITH RODNEY WAYNE ,  STREETT DAREN EUGENE

Inventor： SARTORIUS THOMAS ANDREW ,  SMITH RODNEY WAYNE ,  STREETT DAREN EUGENE

IPC: G06F12/08 ,  G06F12/10

CPC classification number: G06F12/1063 ,  G06F12/0891 ,  G06F2212/1056 ,  G06F2212/683

Abstract: An instruction cache system having a virtually tagged instruction cache which, from a software program perspective, operates as if it were a physically tagged instruction cache is disclosed. The instruction cache system also includes a means for address translation which is responsive to an address translation invalidate instruction and a control logic circuit. The control logic circuit is configured to invalidate an entry in the virtually tagged instruction cache in response to the address translation invalidate instruction.

Abstract translation: 一种具有虚拟标记的指令高速缓存的指令高速缓存系统，其从软件程序的角度来看，如同它是物理标记的指令高速缓存一样被操作。 指令高速缓存系统还包括响应于地址转换无效指令和控制逻辑电路的地址转换装置。 控制逻辑电路被配置为响应于地址转换无效指令使虚拟标记的指令高速缓存中的条目无效。

公开(公告)号：WO2008021763A1

公开(公告)日：2008-02-21

申请号：PCT/US2007/075194

申请日：2007-08-03

Applicant: QUALCOMM INCORPORATED ,  BURKE, Kevin, Charles ,  STEMPEL, Brian, Michael ,  STREETT, Daren, Eugene ,  SAPP, Kevin, Allen ,  DEBRUYNE, Leslie, Mark ,  RIZK, Nabil, Amir ,  SARTORIUS, Thomas, Andrew ,  SMITH, Rodney, Wayne

Inventor： BURKE, Kevin, Charles ,  STEMPEL, Brian, Michael ,  STREETT, Daren, Eugene ,  SAPP, Kevin, Allen ,  DEBRUYNE, Leslie, Mark ,  RIZK, Nabil, Amir ,  SARTORIUS, Thomas, Andrew ,  SMITH, Rodney, Wayne

IPC: G06F11/36

CPC classification number: G06F11/3648

Abstract: A processor is operative to execute two or more instruction sets, each in a different instruction set operating mode. As each instruction is executed, debug circuit comparison the current instruction set operating mode to a target instruction set operating mode sent by a programmer, and outputs an alert or indication in they match. The alert or indication may additionally be dependent upon the instruction address following within a predetermined target address range. The alert or indication may comprise a breakpoint signal that halts execution and/or it is output as an external signal of the processor. The instruction address at which the processor detects a match in the instruction set operating modes may additionally be output. Additionally or alternatively, the alert or indication may comprise starting or stopping a trace operation, causing an exception, or any other known debugger function.

Abstract translation: 处理器可操作以执行两个或更多个指令集，每个指令集在不同的指令集操作模式中。 当执行每个指令时，调试电路将当前指令集操作模式与编程器发送的目标指令集操作模式进行比较，并输出其中的警报或指示。 警报或指示还可以依赖于在预定目标地址范围内的指令地址。 警报或指示可以包括停止执行的断点信号和/或其作为处理器的外部信号输出。 可以另外输出处理器在指令集操作模式中检测到匹配的指令地址。 附加地或替代地，警报或指示可以包括启动或停止跟踪操作，引起异常或任何其他已知的调试器功能。

公开(公告)号：WO2007124307A2

公开(公告)日：2007-11-01

申请号：PCT/US2007/066802

申请日：2007-04-17

Applicant: QUALCOMM INCORPORATED ,  SARTORIUS, Thomas Andrew ,  SMITH, Rodney Wayne ,  STREETT, Daren Eugene

Inventor： SARTORIUS, Thomas Andrew ,  SMITH, Rodney Wayne ,  STREETT, Daren Eugene

CPC classification number: G06F12/1063 ,  G06F12/0891 ,  G06F2212/1056 ,  G06F2212/683

Abstract: An instruction cache system having a virtually tagged instruction cache which, from a software program perspective, operates as if it were a physically tagged instruction cache is disclosed. The instruction cache system also includes a means for address translation which is responsive to an address translation invalidate instruction and a control logic circuit. The control logic circuit is configured to invalidate an entry in the virtually tagged instruction cache in response to the address translation invalidate instruction.

Abstract translation: 公开了一种具有虚拟标记的指令高速缓存的指令高速缓存系统，从软件程序角度来看，其操作就好像它是物理标记的指令高速缓存。 指令高速缓存系统还包括用于地址转换的装置，它响应地址转换无效指令和控制逻辑电路。 控制逻辑电路被配置为响应于地址转换无效指令使虚拟标记的指令高速缓存中的条目无效。