公开(公告)号：WO2011109476A1

公开(公告)日：2011-09-09

申请号：PCT/US2011/026815

申请日：2011-03-02

Applicant: QUALCOMM INCORPORATED ,  CODRESCU, Lucian ,  PLONDKE, Erich James ,  INGLE, Ajay Anant ,  VENKUMAHANTI, Suresh K. ,  TABONY, Charles Joseph

Inventor： CODRESCU, Lucian ,  PLONDKE, Erich James ,  INGLE, Ajay Anant ,  VENKUMAHANTI, Suresh K. ,  TABONY, Charles Joseph

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3853 ,  G06F9/30149

Abstract: A system and method of processing a hierarchical very long instruction word (VLIW) packet is disclosed. In a particular embodiment, a method of processing instructions is disclosed. The method includes receiving a hierarchical VLIW packet of instructions and decoding an instruction from the packet to determine whether the instruction is a single instruction or whether the instruction includes a subpacket that includes a plurality of sub-instructions. The method also includes, in response to determining that the instruction includes the subpacket, executing each of the sub-instructions.

Abstract translation: 公开了一种处理分级非常长的指令字（VLIW）分组的系统和方法。 在特定实施例中，公开了一种处理指令的方法。 该方法包括：接收分层VLIW指令分组，并对来自分组的指令进行解码，以确定该指令是单个指令还是指令是否包括包含多个子指令的子分组。 响应于确定指令包括子分组，该方法还包括执行每个子指令。

公开(公告)号：WO2012151331A1

公开(公告)日：2012-11-08

申请号：PCT/US2012/036196

申请日：2012-05-02

Applicant: QUALCOMM Incorporated ,  PLONDKE, Erich James ,  CODRESCU, Lucian ,  TABONY, Charles Joseph ,  VENKUMAHANTI, Suresh K. ,  INGLE, Ajay Anant

Inventor： PLONDKE, Erich James ,  CODRESCU, Lucian ,  TABONY, Charles Joseph ,  VENKUMAHANTI, Suresh K. ,  INGLE, Ajay Anant

IPC: G06F9/30

CPC classification number: G06F9/30192 ,  G06F9/30167

Abstract: Programs often require constants that cannot be encoded in a native instruction format, such as 32-bits. To provide an extended constant, an instruction packet is formed with constant extender information and a target instruction. The constant extender information encoded as a constant extender instruction provides a first set of constant bits, such as 26-bits for example, and the target instruction provides a second set of constant bits, such as 6-bits. The first set of constant bits are combined with the second set of constant bits to generate an extended constant for execution of the target instruction. The extended constant may be used as an extended source operand, an extended address for memory access instructions, an extended address for branch type of instructions, and the like. Multiple constant extender instructions may be used together to provide larger constants than can be provided by a single extension instruction.

Abstract translation: 程序通常需要不能以本机指令格式编码的常量，例如32位。 为了提供扩展常数，形成具有恒定扩展器信息和目标指令的指令包。 编码为恒定扩展器指令的恒定扩展器信息提供第一组常量位，例如26位，目标指令提供第二组常数位，例如6位。 第一组常数位与第二组常数位组合以产生用于执行目标指令的扩展常数。 扩展常数可以用作扩展源操作数，存储器访问指令的扩展地址，分支类型的指令的扩展地址等。 多个恒定扩展器指令可以一起使用以提供比单个扩展指令可以提供的更大的常数。

公开(公告)号：WO2013013100A1

公开(公告)日：2013-01-24

申请号：PCT/US2012/047488

申请日：2012-07-19

Applicant: QUALCOMM INCORPORATED ,  PLONDKE, Erich, James ,  CODRESCU, Lucian ,  TABONY, Charles, Joseph ,  INGLE, Ajay, Anant ,  VENKUMAHANTI, Suresh, K. ,  MENEZES, Evandro, Carlos

Inventor： PLONDKE, Erich, James ,  CODRESCU, Lucian ,  TABONY, Charles, Joseph ,  INGLE, Ajay, Anant ,  VENKUMAHANTI, Suresh, K. ,  MENEZES, Evandro, Carlos

IPC: G06F9/30

CPC classification number: G06F9/30054 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/322 ,  G06F9/327

Abstract: An apparatus includes a memory that stores an instruction including an opcode and an operand. The operand specifies an immediate value or a register indicator of a register storing the immediate value. The immediate value is usable to identify a function call address. The function call address is selectable from a plurality of function call addresses.

Abstract translation: 一种装置包括存储包含操作码和操作数的指令的存储器。 操作数指定存储立即值的寄存器的立即值或寄存器指示符。 立即值可用于标识函数调用地址。 功能调用地址可以从多个功能调用地址中选择。

公开(公告)号：WO2011063362A1

公开(公告)日：2011-05-26

申请号：PCT/US2010/057685

申请日：2010-11-22

Applicant: QUALCOMM Incorporated ,  PLONDKE, Erich, James ,  CODRESCU, Lucian ,  INGLE, Ajay, Anant ,  ZENG, Mao ,  KOOB, Christopher, Edward ,  TABONY, Charles, Joseph

Inventor： PLONDKE, Erich, James ,  CODRESCU, Lucian ,  INGLE, Ajay, Anant ,  ZENG, Mao ,  KOOB, Christopher, Edward ,  TABONY, Charles, Joseph

IPC: G06F9/30 ,  H04N7/26 ,  H03M7/40

CPC classification number: H03M7/4006 ,  G06F9/30018 ,  G06F9/3895 ,  H04N19/13 ,  H04N19/436 ,  H04N19/44 ,  H04N19/61

Abstract: A dedicated arithmetic decoding instruction is disclosed. In a particular embodiment, an apparatus includes a memory and a processor coupled to the memory. The processor is configured to execute general purpose instructions and to execute a dedicated arithmetic decoding instruction retrieved from the memory.

Abstract translation: 公开了专用算术解码指令。 在特定实施例中，装置包括存储器和耦合到存储器的处理器。 处理器被配置为执行通用指令并且执行从存储器检索的专用算术解码指令。