公开(公告)号：WO2019083642A1

公开(公告)日：2019-05-02

申请号：PCT/US2018/051592

申请日：2018-09-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： WUU, John ,  CIRAULA, Michael K. ,  SCHREIBER, Russell ,  NAFFZIGER, Samuel

IPC: G06F12/02 ,  G06F12/06 ,  G06F3/06

Abstract: A processing system [100] includes a compute die [102] and a stacked memory [104] stacked with the compute die. The stacked memory includes a first memory die [104B] and a second memory die [104A] stacked on top of the first memory die. A parallel access using a single memory address is directed towards different memory banks [206, 208] of the first memory die and the second memory die. The single memory address of the parallel access is swizzled to access the first memory die and the second memory die at different physical locations.