公开(公告)号：WO2017176217A1

公开(公告)日：2017-10-12

申请号：PCT/SG2017/050199

申请日：2017-04-07

Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH

Inventor： DO, Anh Tuan ,  FONG, Xuanyao ,  ZHOU, Jun ,  LIU, Xin ,  HAN, Michael Kim Kwong

IPC: G11C11/15 ,  G11C11/416 ,  G11C11/16 ,  H01L27/105 ,  H01L43/08

Abstract: Various embodiments may provide a circuit arrangement. The circuit arrangement may include a first and a second memory element each having a first electrode and a second electrode, a first access transistor having a first controlled electrode connected to the second electrode of the first memory element, a second access transistor having a first controlled electrode connected to the first electrode of the second memory element, a first bit line connected to the first electrode of the first memory element, and a second bit line connected to the second electrode of the second memory element, wherein current flows of same direction in the first and second memory elements would provide complementary logic states in the first and second memory elements, respectively.

Abstract translation: 各种实施例可以提供电路布置。 该电路装置可以包括第一和第二存储元件，每个存储元件具有第一电极和第二电极，第一存取晶体管具有连接到第一存储元件的第二电极的第一受控电极，第二存取晶体管具有第一受控 连接到第二存储器元件的第一电极的第一位线，连接到第一存储器元件的第一电极的第一位线以及连接到第二存储器元件的第二电极的第二位线，其中电流在 第一和第二存储器元件将分别在第一和第二存储器元件中提供互补的逻辑状态。

公开(公告)号：WO2014200430A1

公开(公告)日：2014-12-18

申请号：PCT/SG2014/000258

申请日：2014-06-05

Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH

Inventor： ZHOU, Jun ,  LIU, Xin

IPC: H03K5/135 ,  H03K5/1534

CPC classification number: G06F1/08 ,  H03K3/0375

Abstract: A method for detecting and correcting an error in a circuit is provided. The circuit is configured to receive an input signal and clock the input signal with a rising and falling timing signal. The method includes detecting late arrival signal transition of the input signal, at an intermediate point of a path, the path being one through which the input signal transits. The method further includes predicting an error in the input signal in response to detecting the late arrival signal transition at the intermediate point of the path. In addition, the method includes correcting the error in the input signal by manipulating the timing signal and/or a supply voltage.

Abstract translation: 提供了一种用于检测和校正电路中的误差的方法。 电路被配置为接收输入信号并且通过上升和下降定时信号对输入信号进行时钟。 该方法包括检测输入信号的延迟到达信号转变，在路径的中间点，路径是输入信号通过的路径。 该方法还包括响应于检测到在路径的中间点的迟到到达信号转变来预测输入信号中的误差。 此外，该方法包括通过操纵定时信号和/或电源电压来校正输入信号中的误差。

公开(公告)号：WO2014200438A1

公开(公告)日：2014-12-18

申请号：PCT/SG2014/000276

申请日：2014-06-12

Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH

Inventor： LIU, Xin ,  ZHOU, Jun

IPC: A61B5/0402 ,  G01R19/25

CPC classification number: A61B5/04012 ,  A61B5/0428 ,  A61B5/0472 ,  A61B5/0476 ,  A61B5/4812 ,  A61B5/4836 ,  A61B5/7203 ,  G01R19/2509

Abstract: An electrocardiogram (ECG) signal processing system is provided. The ECG signal processing system comprises an analog-to-digital converter (ADC) configured to convert an input analog ECG signal into a digital ECG signal, and a digital signal processing engine (DSPE) coupled to the ADC to receive the digital ECG signal. The DSPE is configured to decompose and reconstruct the digital ECG signal. A dynamic system clock source is coupled to the ADC and the DSPE for dynamic signal sampling, the dynamic system clock source clocking the ADC and the DSPE at a first frequency f1 to detect one or more first parameters of the input analog ECG signal and at a second frequency f2 to detect one or more second parameters of the input analog ECG signal.

Abstract translation: 提供心电图（ECG）信号处理系统。 ECG信号处理系统包括被配置为将输入的模拟ECG信号转换为数字ECG信号的模数转换器（ADC）以及耦合到ADC以接收数字ECG信号的数字信号处理引擎（DSPE）。 DSPE被配置为分解和重建数字ECG信号。 动态系统时钟源耦合到ADC和DSPE用于动态信号采样，动态系统时钟源以第一频率f1为ADC和DSPE提供时钟，以检测输入模拟ECG信号的一个或多个第一参数， 第二频率f2以检测输入的模拟ECG信号的一个或多个第二参数。

公开(公告)号：WO2014200429A1

公开(公告)日：2014-12-18

申请号：PCT/SG2014/000257

申请日：2014-06-04

Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH

Inventor： ZHOU, Jun ,  WANG, Chao

IPC: H03K19/0175

CPC classification number: H03K19/0013 ,  H03K3/356165 ,  H03K3/356182 ,  H03K19/017509

Abstract: A circuit arrangement may be provided including a level shifting stage configured to be coupled to a first reference voltage and a second reference voltage. The circuit arrangement may also include a first input electrode in electrical connection with the level shifting stage for coupling a first input voltage and a second input electrode in electrical connection with the level shifting stage for coupling a second input voltage. The level shifting stage may be configured to generate an output voltage above a predetermined output level at the output node due to the first reference voltage when the first input voltage is in the first logic state and the second input voltage is in the second logic state. The circuit arrangement may also include a feedback circuit coupled to the output stage and the level shifting stage and a voltage stabilization circuit coupled to the level shifting stage.

Abstract translation: 可以提供电路装置，其包括电平移位级，配置为耦合到第一参考电压和第二参考电压。 电路装置还可以包括与电平移位级电连接的用于耦合第一输入电压的第一输入电极和与电平移位级电连接的用于耦合第二输入电压的第二输入电极。 电平移位级可以被配置为当第一输入电压处于第一逻辑状态并且第二输入电压处于第二逻辑状态时，由于第一参考电压，在输出节点处产生高于预定输出电平的输出电压。 电路装置还可以包括耦合到输出级和电平移位级的反馈电路以及耦合到电平转换级的稳压电路。

公开(公告)号：WO2019070196A1

公开(公告)日：2019-04-11

申请号：PCT/SG2018/050496

申请日：2018-10-01

Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH

Inventor： ZHOU, Jun ,  LIU, Xin ,  LAN, Jingjing

IPC: H03K5/1252

Abstract: Various embodiments may relate to a clocking circuit arrangement. The clocking circuit arrangement may include a clock source, as well as a global monitoring circuit arrangement including a monitoring tunable clock buffer, a reference clock buffer, a glitch capturing circuit arrangement, and a voltage generation circuit arrangement. The clocking circuit arrangement may further include a main circuit arrangement including one or more further tunable clock buffers.