公开(公告)号：WO2023037093A1

公开(公告)日：2023-03-16

申请号：PCT/GB2022/052164

申请日：2022-08-22

Applicant: ARM LIMITED

Inventor： WHATMOUGH, Paul Nicholas ,  LIU, Zhi-Gang ,  MATTINA, Matthew

IPC: G06F17/16 ,  G06N3/02

Abstract: A matrix multiplication system and method are provided. The system includes a memory that stores one or more weight tensors, a processor and a matrix multiply accelerator (MMA). The processor converts each weight tensor into an encoded block set that is stored in the memory. Each encoded block set includes a number of encoded blocks, and each encoded block includes a data field and an index field. The MMA converts each encoded block set into a reconstructed weight tensor, and convolves each reconstructed weight tensor and an input data tensor to generate an output data matrix.

公开(公告)号：WO2021245370A1

公开(公告)日：2021-12-09

申请号：PCT/GB2021/051222

申请日：2021-05-20

Applicant: ARM LIMITED

Inventor： LIU, Zhi-Gang ,  MATTINA, Matthew

IPC: G06F7/72 ,  G06F7/499 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06F7/02 ,  G06F7/50 ,  G06F9/3893 ,  G06F9/5027 ,  G06N3/0454 ,  G06N3/0481 ,  G06N3/084

Abstract: The present disclosure advantageously provides a modulo operation unit that includes a first input configured to receive operand data, a second input configured to receive modulus data, an initial modulo stage, a sequence of intermediate modulo stages, and a final modulo stage.

公开(公告)号：WO2022112739A1

公开(公告)日：2022-06-02

申请号：PCT/GB2021/052913

申请日：2021-11-11

Applicant: ARM LIMITED

Inventor： LIU, Zhi-Gang ,  MATTINA, Matthew

IPC: G06F17/16 ,  G06N3/04

Abstract: A system and method for multiplying matrices, and method for training a convolutional neural network (CNN), are provided. The system includes a processor and a matrix multiply accelerator (MMA). The processor is configured to generate, based on an input tensor, a number of basic block matrices, each basic block matrix including a number of elements; for each basic block matrix: prune, based on a sparsity value, the elements of the basic block matrix, generate a mask for the basic block matrix, each mask including a number of bits, each bit corresponding to a different element of the basic block matrix, and compress the basic block matrix to generate a compressed basic block matrix having fewer elements than the basic block matrix. The MMA is configured to multiply, based on the masks, the compressed basic block matrices and a weight matrix to generate an output matrix.

公开(公告)号：WO2021181104A1

公开(公告)日：2021-09-16

申请号：PCT/GB2021/050612

申请日：2021-03-11

Applicant: ARM LIMITED

Inventor： LIU, Zhi-Gang ,  MATTINA, Matthew ,  BROWN III, John Fremont

IPC: G06N3/067 ,  G06N3/04 ,  G06N3/08

Abstract: The present disclosure advantageously provides an Optical Hardware Accelerator (OHA) for an Artificial Neural Network (ANN) that includes a communication bus interface, a memory, a controller, and an optical computing engine (OCE). The OCE is configured to execute an ANN model with ANN weights. Each ANN weight includes a quantized phase shift value θ\ and a phase shift value Φ\. The OCE includes a digital-to-optical (D/O) converter configured to generate input optical signals based on the input data, an optical neural network (ONN) configured to generate output optical signals based on the input optical signals, and an optical-to-digital (O/D) converter configured to generate the output data based on the output optical signals. The ONN includes a plurality of optical units (OUs), and each OU includes an optical multiply and accumulate (OMAC) module.