公开(公告)号：WO2023066657A1

公开(公告)日：2023-04-27

申请号：PCT/EP2022/077591

申请日：2022-10-04

Applicant: ASML NETHERLANDS B.V.

Inventor： FANG, Tsung-Pao ,  LIN, Wei-Chou ,  LIN, Hao ,  SONG, Chao

IPC: G03F1/36 ,  G03F1/70 ,  G03F7/20

Abstract: Described herein is a method for grouping patterns associated with one or more design layouts of a semiconductor. The method involves obtaining a set of patterns (e.g., from one or more design layouts), where a pattern of the set of patterns includes a non-intersected feature portion (e.g., parallel bars) within a bounding box of the pattern. A non-intersected feature portion of a pattern is encoded to a pattern representation having elements, where each element has a first component indicating a type of an individual non-intersected feature portion, and a second component indicating a width of the individual non-intersected feature portion projected along a designated edge of an area enclosing the pattern. The set of patterns are grouped into one or more groups by comparing the pattern representations associated the set of patterns.