公开(公告)号：WO2003088489A3

公开(公告)日：2003-10-23

申请号：PCT/US2003/011047

申请日：2003-04-11

Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION

Inventor： MCDONALD, James J., II. ,  HULFACHOR, Ronald, B. ,  WUNDERLICH, Jim

IPC: G11B5/09

Abstract: A phase locked loop circuit is used to provide timing clocks for bit recovery from a serial data flow. The system locked to a SYNC signal, preferably a lower frequency fifty percent duty cycle square wave with a period equal to the time of a fully framed serial data word. When a start signal transition is detected the system is prevented from trying to lock onto the data signal edge transitions. But, the system provides a signal suitable for clockingin the individual data bits.

公开(公告)号：WO2003088489A2

公开(公告)日：2003-10-23

申请号：PCT/US2003/011047

申请日：2003-04-11

Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION

Inventor： MCDONALD, James J., II. ,  HULFACHOR, Ronald, B. ,  WUNDERLICH, Jim

IPC: H03L

CPC classification number: H03L7/0891 ,  H03L7/095 ,  H03L7/0995 ,  H03L7/10 ,  H03L2207/14 ,  H04L7/033 ,  H04L7/044 ,  H04L7/10

Abstract: A phase locked loop circuit is used to provide timing clocks for bit recovery from a serial data flow. The system locked to a SYNC signal, preferably a lower frequency fifty percent duty cycle square wave with a period equal to the time of a fully framed serial data word. When a start signal transition is detected the system is prevented from trying to lock onto the data signal edge transitions. But, the system provides a signal suitable for clockingin the individual data bits.

Abstract translation: 锁相环电路用于提供从串行数据流中进行位恢复的定时时钟。 该系统锁定为SYNC信号，优选地是具有等于完全成帧的串行数据字的时间的周期的较低频率百分之五十的占空比方波。 当检测到启动信号转换时，系统被阻止试图锁定到数据信号边沿转换。 但是，该系统提供适合于在各个数据位上定时的信号。