公开(公告)号：WO2023078955A1

公开(公告)日：2023-05-11

申请号：PCT/EP2022/080592

申请日：2022-11-02

Applicant: GRAPHCORE LIMITED

Inventor： CUNNINGHAM, Graham ,  YASINE, Hachem ,  WILKINSON, Daniel John Pelham

IPC: H04L49/253

Abstract: A hardware module comprises at least a first ingress buffer and a second ingress buffer, where the second ingress buffer holds data packets from multiple source components. The module first determines that the packet at the head of the first ingress buffer is targeting the first destination. To ensure fairness between one or more sources providing data to the first ingress buffer and the plurality of sources providing data to the second ingress buffer, processing circuitry examines source identifiers in packets held in the second ingress buffer and selects between the buffers so as to arbitrate between the sources. In some embodiments, the examination of the source identifiers provides statistics for a weighted round robin between the ingress buffers. In other embodiments, the source identifier of whichever packet is currently at the head of the second ingress buffer is used to perform a simple round robin between the sources.