公开(公告)号：WO2023030653A1

公开(公告)日：2023-03-09

申请号：PCT/EP2021/074400

申请日：2021-09-03

Applicant: IMEC VZW ,  HUAWEI TECHNOLOGIES CO., LTD.

Inventor： RAWAT, Amita ,  WU, Hao ,  HELLINGS, Geert ,  BHUWALKA, Krishna Kumar

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/775

Abstract: A nanostructure according to the invention comprises a pair of nanosheet or nanowire transistors (1,1') configured to conduct charge by carriers of opposite polarity (such as n and p type carriers), wherein one of the two transistors is provided with inner spacers (10) and the other is not provided with inner spacers. The inventors found that depending on the type of charge carrier, the omission of the inner spacers may offer an unexpected improvement in the admittance of the device that outweighs the negative impact of the inner spacer omission. This is the case for example in a Si-channel PMOS nanosheet transistor (1'), whereas in a Si channel NMOS nanosheet transistor (1), the omission of the inner spacers has a negative effect on the parasitic capacitance that outweighs any benefits of the inner spacer omission. A preferred embodiment of the invention therefore includes complementary NMOS and PMOS silicon transistors (1,1'), wherein the NMOS is provided with inner spacers (10), whereas the PMOS is not provided with inner spacers.