公开(公告)号：WO2006060237A3

公开(公告)日：2006-09-14

申请号：PCT/US2005042314

申请日：2005-11-17

Applicant: INTEL CORP ,  POISNER DAVID ,  STEVENS WILLIAM

Inventor： POISNER DAVID ,  STEVENS WILLIAM

IPC: G06F11/14

CPC classification number: G06F11/1441 ,  G06F12/0804

Abstract: In some embodiment, an arrangement is provided to prevent a loss of data in a memory due to a power failure for a computing system. When the power failure occurs, any pending memory write operations may be completed and dirty cache lines may be flushed back to the memory. Subsequently, the computing system may be put into a loss-prevention state, under which power may be turned off for all components in the computing system except the memory. The memory is powered by a battery pack which includes batteries and is in a self refresh state. When the power returns, applications and operating systems running in the computing system may resume what is left out when the power supply failure occurs, based at least in part on data retained in the memory. Other embodiments are described and claimed.

Abstract translation: 在一些实施例中，提供了一种布置，以防止由于计算系统的电源故障导致的存储器中的数据丢失。 当发生电源故障时，可能会完成任何未完成的存储器写操作，并将脏高速缓存行刷新回存储器。 随后，计算系统可以被置于防止丢失状态，在该状态下，计算系统中除了存储器之外的所有组件都可以关闭电源。 存储器由包括电池并且处于自刷新状态的电池组供电。 当电力返回时，运行在计算系统中的应用程序和操作系统可以至少部分地基于保存在存储器中的数据来恢复发生电源故障时所剩下的内容。 描述和要求保护其他实施例。

公开(公告)号：WO03069471A2

公开(公告)日：2003-08-21

申请号：PCT/US0302376

申请日：2003-01-24

Applicant: INTEL CORP

Inventor： KRITHIVAS RAMAMURTHY ,  BRANNOCK KIRK ,  HALE ROBERT ,  FISH ANDREW ,  STEVENS WILLIAM

IPC: G06F9/445

CPC classification number: G06F8/54 ,  G06F9/4401

Abstract: A BIOS includes a core and multiple modules. The modules include both those that are platform specific and those that are not platform specific. Each module has a standard interface that allows the core (or other module) to call the module. A platform vendor constructs a BIOS by selecting modules from one or more vendors, which when executed can select modules that are suitable for the platform the BIOS resides in.

Abstract translation: BIOS包括核心和多个模块。 这些模块包括那些具有平台特性的模块，以及不具有平台特性的模块。 每个模块都有一个标准接口，允许核心（或其他模块）调用该模块。 平台供应商通过从一个或多个供应商中选择模块来构建BIOS，当被执行时可以选择适合于BIOS所在平台的模块。

公开(公告)号：WO2004046920A2

公开(公告)日：2004-06-03

申请号：PCT/US0334808

申请日：2003-10-30

Applicant: INTEL CORP

Inventor： DATTA SHAM ,  ZIMMER VINCENT ,  VAID KUSHAGRA ,  STEVENS WILLIAM ,  SANTONI AMY

IPC: G06F9/445 ,  G06F12/08 ,  G06F12/12

CPC classification number: G06F12/126 ,  G06F9/4403 ,  G06F12/0862 ,  G06F2212/2515

Abstract: In one embodiment, a computer boot method allows choosing a predetermined data block alignment for a cache that has multiple cross processor interactions. A cache RAM column of a cache as RAM system is loaded with a tag to prevent unintended cache line evictions, and boot code is executed, with the preloaded cache RAM appearing to the exe­cuting boot code stream as a memory store.

Abstract translation: 在一个实施例中，计算机引导方法允许为具有多个交叉处理器交互的高速缓存选择预定数据块对齐。 作为RAM系统的缓存的高速缓存RAM列被加载有标签以防止意外的高速缓存行驱逐，并且执行引导代码，其中预先加载的高速缓存RAM作为存储器存储器显示在执行的引导代码流中。