公开(公告)号：WO2023091258A1

公开(公告)日：2023-05-25

申请号：PCT/US2022/046732

申请日：2022-10-14

Applicant: INTEL CORPORATION

Inventor： MOHAPATRA, Debabrata ,  RAHA, Arnab ,  MATHAIKUTTY, Deepak Abraham ,  SUNG, Raymond Jit-Hung ,  BRICK, Cormac Michael

IPC: G06F9/50 ,  G06N3/04 ,  G06F9/30 ,  G06F7/544

Abstract: There is disclosed a system and method of performing an artificial intelligence (AI) inference, including: programming an AI accelerator circuit to solve an AI problem with a plurality of layer-specific register file (RF) size allocations, wherein the AI accelerator circuit comprises processing elements (PEs) with respective associated RFs, wherein the RFs individually are divided into K sub-banks of size B bytes, wherein B and K are integers, and wherein the RFs include circuitry to individually allocate a sub-bank to one of input feature (IF), output feature (OF), or filter weight (FL), and wherein programming the plurality of layer-specific RF size allocations comprises accounting for sparse data within the layer; and causing the AI accelerator circuit to execute the AI problem, including applying the layer-specific RF size allocations at run-time.