公开(公告)号：WO2013148739A1

公开(公告)日：2013-10-03

申请号：PCT/US2013/033951

申请日：2013-03-26

Applicant: INTEL CORPORATION

Inventor： CHAN, Hiu-Fai R. ,  WONG, Samuel ,  CHENG, Scott W. ,  QURASHI, Mohmad I.

IPC: H04N7/26

CPC classification number: H04N19/90 ,  H04N19/91

Abstract: CABAC coefficient decoding may be increased to two bins per clock. Since coefficients comprise most of the bitstream, this improvement almost doubles the CABAC decoding for a low quantization parameter bitstream (with lots of coefficients).

Abstract translation: CABAC系数解码可以每个时钟增加到两个箱。 由于系数包括大多数比特流，所以这种改进对于低量化参数比特流（具有大量系数）几乎使CABAC解码加倍。

公开(公告)号：WO2013148737A1

公开(公告)日：2013-10-03

申请号：PCT/US2013/033949

申请日：2013-03-26

Applicant: INTEL CORPORATION

Inventor： QURASHI, Mohmad, I. ,  WONG, Samuel ,  CHAN, Hiu-fai, R. ,  CHENG, Scott, W.

IPC: H04N7/26

CPC classification number: H04N19/44 ,  H04N19/91

Abstract: Context-adaptive variable length bitstream decoding performance may be improved and power consumption reduced by pushing the variable length decoding beyond one syntax element per clock pulse.

Abstract translation: 可以通过将可变长度解码超过每个时钟脉冲一个语法元素来改善上下文自适应可变长度比特流解码性能并降低功耗。

公开(公告)号：WO2013074088A1

公开(公告)日：2013-05-23

申请号：PCT/US2011/060779

申请日：2011-11-15

Applicant: INTEL CORPORATION ,  WONG, Samuel ,  CHAN, Hiu-Fai, R. ,  QURASHI, Mohmad, I.

Inventor： WONG, Samuel ,  CHAN, Hiu-Fai, R. ,  QURASHI, Mohmad, I.

IPC: H04N7/24

CPC classification number: H04N19/00 ,  H04N19/436 ,  H04N19/61 ,  H04N19/91

Abstract: Systems, devices and methods are described including using, during a single clock cycle, one Context-Based Adaptive Arithmetic Coding (CABAC) engine to encode one bin value and another CABAC engine to encode another bin value. The probability state index of each CABAC engine may provided to the other CABAC engine when the bin values are encoded.

Abstract translation: 描述了系统，设备和方法，包括在单个时钟周期期间使用一个基于上下文的自适应算术编码（CABAC）引擎来对一个bin值进行编码，而另一个CABAC引擎用于编码另一个bin值。 当二进制值被编码时，每个CABAC引擎的概率状态索引可以提供给另一个CABAC引擎。

公开(公告)号：WO2006050290A2

公开(公告)日：2006-05-11

申请号：PCT/US2005/039325

申请日：2005-10-27

Applicant: INTEL CORPORATION ,  NICKERSON, Brian ,  WONG, Samuel ,  CHAUDHURI, Santanu ,  LIU, Jonathan ,  KURUPATI, Sreenath

Inventor： NICKERSON, Brian ,  WONG, Samuel ,  CHAUDHURI, Santanu ,  LIU, Jonathan ,  KURUPATI, Sreenath

IPC: H04N7/01

CPC classification number: H04N7/0125 ,  G09G5/391 ,  G09G5/395 ,  G09G2340/0407 ,  H04N7/0135

Abstract: A portion of a video frame is transferred via a memory burst transfer, from memory to an on-chip buffer. The on-chip buffer has a width that is the same as the memory burst width for the memory. Video processing is performed upon the transferred portion. Other embodiments are also described and claimed.

Abstract translation: 视频帧的一部分通过存储器突发传输从存储器传输到片上缓冲器。 片上缓冲器的宽度与内存的内存突发宽度相同。 视频处理在被传送的部分上执行。 其他实施例也被描述和要求保护。

公开(公告)号：WO2006036571A1

公开(公告)日：2006-04-06

申请号：PCT/US2005/032932

申请日：2005-09-13

Applicant: INTEL CORPORATION ,  KURUPATI, Sreenath ,  NICKERSON, Brian ,  WONG, Samuel ,  CHAUDHARI, Sunil ,  LIU, Jonathan

Inventor： KURUPATI, Sreenath ,  NICKERSON, Brian ,  WONG, Samuel ,  CHAUDHARI, Sunil ,  LIU, Jonathan

IPC: G06T3/40

CPC classification number: G06T3/403

Abstract: A method and apparatus for hardware-base edge handling in video post-processing. In one embodiment, the method includes the identification of at least one unstored input pixel required to compute an output pixel during output pixel computation. Once identified, a pixel value is generated for the at least one unstored input pixel according to a detected edge handling mode. The generation of the pixel value for the unstored input pixel is performed, in one embodiment, if a position of the unstored input pixel is outside a pixel frame boundary. For example, in one embodiment, for output pixel computation of a scaling operation, the frame boundaries include a left (top) edge and a right (bottom) edge for which input pixels required to compute output pixels at or near the frame boundaries do not exist. Other embodiments are described and claimed.

Abstract translation: 一种用于视频后处理中的硬件边缘处理的方法和装置。 在一个实施例中，该方法包括在输出像素计算期间识别计算输出像素所需的至少一个未输入输入像素。 一旦被识别，根据检测到的边缘处理模式，为至少一个未填充的输入像素生成像素值。 在一个实施例中，如果无输入输入像素的位置在像素帧边界之外，则执行无输入输入像素的像素值的生成。 例如，在一个实施例中，对于缩放操作的输出像素计算，帧边界包括左边（上）边和右（底）边，对于边缘边缘或其附近计算输出像素所需的输入像素 存在。 描述和要求保护其他实施例。