公开(公告)号：WO2013101159A1

公开(公告)日：2013-07-04

申请号：PCT/US2011/068042

申请日：2011-12-30

Applicant: INTEL CORPORATION ,  KESLING, Dawson ,  SKINNER, Harry

Inventor： KESLING, Dawson ,  SKINNER, Harry

IPC: H04B15/04 ,  H03L7/00 ,  H04B1/69

CPC classification number: H04B1/7097 ,  H04B15/04

Abstract: An apparatus, system, and method, the method including receiving clock frequency parameter information for at least one clock source; receiving radio parameter information for at least one radio receiver; determining one or more spread spectrum clocking (SSC) profiles for the at least one clock source and the at least one radio receiver, each SSC profile to reduce radio frequency interference between the clock and radio receivers; and storing the SSC profiles.

Abstract translation: 一种装置，系统和方法，所述方法包括：接收至少一个时钟源的时钟频率参数信息; 接收至少一个无线电接收机的无线电参数信息; 确定所述至少一个时钟源和所述至少一个无线电接收机的一个或多个扩频时钟（SSC）简档，每个SSC简档以减少所述时钟和无线电接收机之间的射频干扰; 并存储SSC配置文件。

公开(公告)号：WO2013048537A1

公开(公告)日：2013-04-04

申请号：PCT/US2011/054498

申请日：2011-10-01

Applicant: INTEL CORPORATION ,  KESLING, Dawson ,  FALCONER, Maynard C. ,  SLATTERY, Kevin P. ,  SKINNER, Harry G.

Inventor： KESLING, Dawson ,  FALCONER, Maynard C. ,  SLATTERY, Kevin P. ,  SKINNER, Harry G.

IPC: H04B15/00

CPC classification number: H03M7/02 ,  H04L27/3411

Abstract: A method for managing information includes receiving bits of data, determining phasors for bits at only one frequency of a transmission spectrum, combining the phasors of bits that form a phasor having a spectral energy that lies within a predetermined range, and forming a codeword from the bits of the combined phasors.

Abstract translation: 一种用于管理信息的方法包括接收数据位，仅在传输频谱的一个频率处确定位的相量，组合具有处于预定范围内的频谱能量的相量的位的相量，以及从 组合相量的位。

公开(公告)号：WO2007050882A3

公开(公告)日：2007-05-03

申请号：PCT/US2006/041991

申请日：2006-10-26

Applicant: INTEL CORPORATION ,  MOHANAVELU, Ravindran ,  MARTIN, Aaron ,  KESLING, Dawson ,  SALMON, Joe ,  UR RASHID, Mamun

Inventor： MOHANAVELU, Ravindran ,  MARTIN, Aaron ,  KESLING, Dawson ,  SALMON, Joe ,  UR RASHID, Mamun

IPC: G06F1/04 ,  H03K19/0175

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for a clocking architecture using a bidirectional clock. In an embodiment, a chip includes a bidirectional clock port capable of being statically configured to receive or to transmit a reference clock. In one embodiment, the chip includes a first port to receive data and a second port, wherein the chip repeats at least a portion of the data that it receives on the first port to a transmitter at the second port. Other embodiments are described and claimed.