公开(公告)号：WO2003019386A1

公开(公告)日：2003-03-06

申请号：PCT/US2002/025090

申请日：2002-08-06

Applicant: INTEL CORPORATION (a Delaware Corporation)

Inventor： CRETA, Kenneth ,  BELL, Dennis ,  BLANKENSHIP, Robert ,  CONGDON, Bradford ,  GEORGE, Robert ,  JANUARY, Duane

IPC: G06F12/08

CPC classification number: G06F12/0848 ,  G06F12/0802 ,  G06F12/0833 ,  G06F13/4059

Abstract: A caching input/output hub includes a host interface to connect with a host. At least one input/output interface is provided to connect with an input/output device. A write cache manages memory writes initiated by the input/output device. At least one read cache, separate from the write cache, provides a low-latency copy of data that is most likely to be used. The at least one read cache is in communication with the write cache. A cache directory is also provided to track cache lines in the write cache and the at least one read cache. The cache directory is in communication with the write cache and the at least one read cache.

Abstract translation: 缓存输入/输出集线器包括与主机连接的主机接口。 提供至少一个输入/输出接口以与输入/输出设备连接。 写缓存管理由输入/输出设备发起的存储器写入。 与写缓存分开的至少一个读缓存提供了最可能使用的低延迟数据副本。 至少一个读高速缓存与写高速缓存通信。 还提供缓存目录以跟踪写入高速缓存和至少一个读取高速缓存中的高速缓存行。 缓存目录与写缓存和至少一个读高速缓存通信。