公开(公告)号：WO2023003938A1

公开(公告)日：2023-01-26

申请号：PCT/US2022/037686

申请日：2022-07-20

Applicant: META PLATFORMS TECHNOLOGIES, LLC

Inventor： CHILDRESS, Kimberly Kay ,  BOROMAND, Arman ,  PURVIS, Lafe Joseph II ,  VADIEE, Ehsan ,  PARK, Namseok ,  OUDERKIRK, Andrew John ,  RAO, Tingling

IPC: C30B7/00 ,  C30B7/14 ,  C30B27/00 ,  C30B29/54 ,  G02B1/04 ,  G02B5/30

Abstract: An organic thin film includes an organic crystalline phase, where the organic crystalline phase defines a surface having a surface roughness (Ra) of less than approximately 10 micrometers over an area of at least approximately 1 cm2. The organic thin film may be manufactured from an organic precursor and a non-volatile medium material that is configured to mediate the surface roughness of the organic crystalline phase during crystal nucleation and growth. The thin film may be formed using a suitably shaped mold, for example, and the non-volatile medium material may be disposed between a layer of the organic precursor and the mold during processing.

公开(公告)号：WO2022245684A1

公开(公告)日：2022-11-24

申请号：PCT/US2022/029354

申请日：2022-05-14

Applicant: META PLATFORMS TECHNOLOGIES, LLC

Inventor： OUDERKIRK, Andrew John ,  SCHELLER, Maik Andre ,  VADIEE, Ehsan ,  GOWARD, John ,  TYAGI, Anurag ,  PETERSON, Jonathan Robert ,  LIAO, Christopher Yuan Ting

IPC: H01L31/0475 ,  H01L31/167 ,  H01L31/0232 ,  H01L31/12 ,  H01S5/042 ,  H01L31/101

Abstract: A method of forming a high voltage optical transformer includes forming a via through a transparent carrier wafer, forming a conductive layer within the via, bonding a solid state lighting (SSL) package to a first side of the carrier wafer, and bonding a photovoltaic (PV) wafer to a second side of the carrier wafer opposite to the first side. The photovoltaic wafer may include an active area and a conductive area located outside of the active area that is in electrical contact with the conductive layer. The method further includes forming both an SSL contact with the solid state lighting package and a PV contact with the conductive layer on the same side of the carrier wafer.