公开(公告)号：WO2021263277A1

公开(公告)日：2021-12-30

申请号：PCT/US2021/070761

申请日：2021-06-23

申请人： MICROCHIP TECHNOLOGY INCORPORATED

发明人： DEVULAPALLI, Sridhar ,  RUSSELL, Daniel J. ,  CHEREK, Brian ,  KLEIN, Michael

IPC分类号： H03K19/0185 ,  H03K19/00 ,  H03K19/0013 ,  H03K19/018521 ,  H03K3/037

摘要： An input circuit that recognizes (e.g., buffers) logic level signals (e.g., of an input signal) represented by voltage levels that are lower than a supply voltage of an input circuit, and that exhibits static current draw immunity during stable states of an input signal. In one or more examples, series inverters are provided to buffer an input node and an output node of the input circuit. A voltage domain at the input circuit or output node may be higher than a voltage domain at the input node. Power supply to a first inverter of the series inverters may be turned OFF at least partially responsive to an indication that an output signal is a logic high; and power supply to the first inverter of the series inverters may be turned ON at least partially responsive to an indication that the output signal is a logic low. A third inverter may be maintained utilizing an input signal voltage to detect a falling edge of the input signal and turn ON power supply to the first inverter at least partially responsive thereto.