Abstract:
A device includes a routing buffer (48). The routing buffer (48) includes a first port configured to receive a signal relating to an analysis of at least a portion of a data stream. The routing buffer (48) also includes a second port configured to selectively provide the signal to a first routing line of a block (32) of a state machine at a first time. The routing buffer (48) further includes a third port configured to selectively provide the signal to a second routing line of the block (32) of the state machine at the first time.
Abstract:
A device (14), includes an instruction buffer (133). The instruction buffer (133) is configured to store instructions related to at least a portion of a data stream to be analyzed by a state machine engine as the device (14). The state machine engine includes configurable elements (60) configured to analyze the at least a portion of a data stream and to selectively output the result of the analysis. Additionally, the instruction buffer (133) is configured to receive the indications as part of a direct memory access (DMA) transfer.
Abstract:
Apparatus, systems, and methods for a compiler are disclosed. One such compiler parses a human readable expression into a syntax tree and converts the syntax tree into an automaton having in-transitions and out-transitions. Converting can include unrolling the quantification as a function of in-degree limitations wherein in-degree limitations includes a limit on the number of transitions into a state of the automaton. The compiler can also convert the automaton into an image for programming a parallel machine, and publishes the image. Additional apparatus, systems, and methods are disclosed.
Abstract:
A device (14) includes a plurality of blocks (32). Each block (32) of the plurality of blocks (32) includes a plurality of rows (38). Each row (38) of the plurality of rows (38) includes a plurality of configurable elements (60) and a routing line (214), whereby each configurable element (60) of the plurality of configurable elements (60) includes a data analysis element (32) comprising a plurality of memory cells (80), wherein the data analysis element (32) is configured to analyze at least a portion of a data stream and to output a result of the analysis. Each configurable element 32) of the plurality of configurable elements (60) also includes a multiplexer (78) configured to transmit the result to the routing line (214).
Abstract:
Apparatus, systems, and methods for a compiler are described. One such compiler generates machine code corresponding to a set of elements including a general purpose element and a special purpose element. The compiler identifies a portion in an arrangement of relationally connected operators that corresponds to a special purpose element. The compiler also determines whether the portion meets a condition to be mapped to the special purpose element. The compiler also converts the arrangement into an automaton comprising a plurality of states, wherein the portion is converted using a special purpose state that corresponds to the special purpose element if the portion meets the condition. The compiler also converts the automaton into machine code. Additional apparatus, systems, and methods are disclosed.
Abstract:
Disclosed are methods and devices, among which is a device that includes a finite state machine lattice (30). The lattice (30) may include a programmable Boolean logic cell (58B) that may be programmed to perform various logic functions on a data stream. The programmability includes an inversion of a first input to the Boolean logic cell (58B), an inversion of a last output of the Boolean logic cell (58B), and a selection of an AND gate or an OR gate as a final output of the Boolean logic cell (58B). The Boolean logic cell (58B) also includes end of data circuitry configured to cause the Boolean logic cell (58B) to only output after an end of data signifying the end of a data stream is received at the Boolean logic cell (58B).
Abstract:
Disclosed are methods and devices, among which is a device that includes a finite state machine lattice (30). The lattice (30) may include a counter (58) suitable for counting a number of times a programmable element (34, 36) in the lattice (30) detects a condition. The counter (58) may be configured to output in response to counting the condition was detected a certain number of times. For example, the counter (58) may be configured to output in response to determining a condition was detected at least (or no more than) the certain number of times, determining the condition was detected exactly the certain number of times, or determining the condition was detected within a certain range of times. The counter (58) may be coupled to other counters (58) in the device for determining high-count operations and/or certain quantifiers.
Abstract:
Embodiments of a system and method for generating an image configured to program a parallel machine from source code are disclosed. One such parallel machine includes a plurality of state machine elements (SMEs) grouped into pairs, such that SMEs in a pair have a common output. One such method includes converting source code into an automaton comprising a plurality of interconnected states, and converting the automaton into a netlist comprising instances corresponding to states in the automaton, wherein converting includes pairing states corresponding to pairs of SMEs based on the fact that SMEs in a pair have a common output. The netlist can be converted into the image and published.
Abstract:
Apparatus, systems, and methods for a compiler are described. One such compiler converts source code into an automaton comprising states and transitions between the states, wherein the states in the automaton include a special purpose state that corresponds to a special purpose hardware element. The compiler converts the automaton into a netlist, and places and routes the netlist to provide machine code for configuring a target device.