METHODS AND SYSTEMS FOR ROUTING IN A STATE MACHINE
    1.
    发明申请
    METHODS AND SYSTEMS FOR ROUTING IN A STATE MACHINE 审中-公开
    用于在状态机中路由的方法和系统

    公开(公告)号:WO2013090096A1

    公开(公告)日:2013-06-20

    申请号:PCT/US2012/068011

    申请日:2012-12-05

    Abstract: A device includes a routing buffer (48). The routing buffer (48) includes a first port configured to receive a signal relating to an analysis of at least a portion of a data stream. The routing buffer (48) also includes a second port configured to selectively provide the signal to a first routing line of a block (32) of a state machine at a first time. The routing buffer (48) further includes a third port configured to selectively provide the signal to a second routing line of the block (32) of the state machine at the first time.

    Abstract translation: 一种设备包括路由缓冲器(48)。 路由缓冲器(48)包括被配置为接收与数据流的至少一部分的分析有关的信号的第一端口。 路由缓冲器(48)还包括被配置为在第一时间将信号选择性地提供给状态机的块(32)的第一路由线的第二端口。 路由缓冲器(48)还包括被配置为在第一时间向状态机的块(32)的第二路由线选择性地提供信号的第三端口。

    SYSTEMS AND DEVICES FOR ACCESSING A STATE MACHINE
    2.
    发明申请
    SYSTEMS AND DEVICES FOR ACCESSING A STATE MACHINE 审中-公开
    用于访问状态机的系统和设备

    公开(公告)号:WO2016109570A1

    公开(公告)日:2016-07-07

    申请号:PCT/US2015/067914

    申请日:2015-12-29

    Abstract: A device (14), includes an instruction buffer (133). The instruction buffer (133) is configured to store instructions related to at least a portion of a data stream to be analyzed by a state machine engine as the device (14). The state machine engine includes configurable elements (60) configured to analyze the at least a portion of a data stream and to selectively output the result of the analysis. Additionally, the instruction buffer (133) is configured to receive the indications as part of a direct memory access (DMA) transfer.

    Abstract translation: 一种设备(14),包括指令缓冲器(133)。 指令缓冲器(133)被配置为存储与状态机引擎要分析的数据流的至少一部分相关的指令作为设备(14)。 状态机引擎包括被配置为分析数据流的至少一部分并且选择性地输出分析结果的可配置元件(60)。 另外,指令缓冲器(133)被配置为接收作为直接存储器访问(DMA)传送的一部分的指示。

    UNROLLING QUANTIFICATIONS TO CONTROL IN-DEGREE AND/OR OUT DEGREE OF AUTOMATON

    公开(公告)号:WO2012103148A3

    公开(公告)日:2012-08-02

    申请号:PCT/US2012/022441

    申请日:2012-01-24

    Abstract: Apparatus, systems, and methods for a compiler are disclosed. One such compiler parses a human readable expression into a syntax tree and converts the syntax tree into an automaton having in-transitions and out-transitions. Converting can include unrolling the quantification as a function of in-degree limitations wherein in-degree limitations includes a limit on the number of transitions into a state of the automaton. The compiler can also convert the automaton into an image for programming a parallel machine, and publishes the image. Additional apparatus, systems, and methods are disclosed.

    DEVICES FOR TIME DIVISION MULTIPLEXING OF STATE MACHINE ENGINE SIGNALS
    4.
    发明申请
    DEVICES FOR TIME DIVISION MULTIPLEXING OF STATE MACHINE ENGINE SIGNALS 审中-公开
    国家机器发动机信号时间分段多路复用装置

    公开(公告)号:WO2016109571A1

    公开(公告)日:2016-07-07

    申请号:PCT/US2015/067915

    申请日:2015-12-29

    Abstract: A device (14) includes a plurality of blocks (32). Each block (32) of the plurality of blocks (32) includes a plurality of rows (38). Each row (38) of the plurality of rows (38) includes a plurality of configurable elements (60) and a routing line (214), whereby each configurable element (60) of the plurality of configurable elements (60) includes a data analysis element (32) comprising a plurality of memory cells (80), wherein the data analysis element (32) is configured to analyze at least a portion of a data stream and to output a result of the analysis. Each configurable element 32) of the plurality of configurable elements (60) also includes a multiplexer (78) configured to transmit the result to the routing line (214).

    Abstract translation: 装置(14)包括多个块(32)。 多个块(32)中的每个块(32)包括多个行(38)。 多行(38)中的每行(38)包括多个可配置元件(60)和布线线(214),由此多个可配置元件(60)中的每个可配置元件(60)包括数据分析 元件(32),其包括多个存储器单元(80),其中所述数据分析元件(32)被配置为分析数据流的至少一部分并输出所述分析结果。 多个可配置元件(60)的每个可配置元件32)还包括多路复用器(78),其经配置以将结果发送到路由线路(214)。

    UTILIZING SPECIAL PURPOSE ELEMENTS TO IMPLEMENT A FSM

    公开(公告)号:WO2012103146A3

    公开(公告)日:2012-08-02

    申请号:PCT/US2012/022439

    申请日:2012-01-24

    Abstract: Apparatus, systems, and methods for a compiler are described. One such compiler generates machine code corresponding to a set of elements including a general purpose element and a special purpose element. The compiler identifies a portion in an arrangement of relationally connected operators that corresponds to a special purpose element. The compiler also determines whether the portion meets a condition to be mapped to the special purpose element. The compiler also converts the arrangement into an automaton comprising a plurality of states, wherein the portion is converted using a special purpose state that corresponds to the special purpose element if the portion meets the condition. The compiler also converts the automaton into machine code. Additional apparatus, systems, and methods are disclosed.

    BOOLEAN LOGIC IN A STATE MACHINE LATTICE
    6.
    发明申请
    BOOLEAN LOGIC IN A STATE MACHINE LATTICE 审中-公开
    BOOLEAN逻辑在一个状态机床

    公开(公告)号:WO2013090092A1

    公开(公告)日:2013-06-20

    申请号:PCT/US2012/067992

    申请日:2012-12-05

    Abstract: Disclosed are methods and devices, among which is a device that includes a finite state machine lattice (30). The lattice (30) may include a programmable Boolean logic cell (58B) that may be programmed to perform various logic functions on a data stream. The programmability includes an inversion of a first input to the Boolean logic cell (58B), an inversion of a last output of the Boolean logic cell (58B), and a selection of an AND gate or an OR gate as a final output of the Boolean logic cell (58B). The Boolean logic cell (58B) also includes end of data circuitry configured to cause the Boolean logic cell (58B) to only output after an end of data signifying the end of a data stream is received at the Boolean logic cell (58B).

    Abstract translation: 公开的方法和装置,其中包括有限状态机格(30)的装置。 格(30)可以包括可编程布尔逻辑单元(58B),其可被编程为在数据流上执行各种逻辑功能。 可编程性包括对布尔逻辑单元(58B)的第一输入的反转,布尔逻辑单元(58B)的最后输出的反转,以及与门或或门的选择作为 布尔逻辑单元(58B)。 布尔逻辑单元(58B)还包括数据电路的末端,其配置用于仅在布尔逻辑单元(58B)接收到表示数据流结束的数据结束之后才输出布尔逻辑单元(58B)。

    COUNTER OPERATION IN A STATE MACHINE LATTICE
    7.
    发明申请
    COUNTER OPERATION IN A STATE MACHINE LATTICE 审中-公开
    状态机计数器中的计数器运行

    公开(公告)号:WO2013090091A2

    公开(公告)日:2013-06-20

    申请号:PCT/US2012/067988

    申请日:2012-12-05

    Abstract: Disclosed are methods and devices, among which is a device that includes a finite state machine lattice (30). The lattice (30) may include a counter (58) suitable for counting a number of times a programmable element (34, 36) in the lattice (30) detects a condition. The counter (58) may be configured to output in response to counting the condition was detected a certain number of times. For example, the counter (58) may be configured to output in response to determining a condition was detected at least (or no more than) the certain number of times, determining the condition was detected exactly the certain number of times, or determining the condition was detected within a certain range of times. The counter (58) may be coupled to other counters (58) in the device for determining high-count operations and/or certain quantifiers.

    Abstract translation: 公开的方法和装置,其中包括有限状态机格(30)的装置。 网格(30)可以包括适于对网格(30)中的可编程元件(34,36)检测到条件的次数进行计数的计数器(58)。 计数器(58)可以被配置为响应于计数而输出,条件被检测到一定次数。 例如,计数器(58)可以被配置为响应于确定至少(或不多于)一定次数的检测到的条件而输出,确定条件被精确地检测到一定次数,或者确定 在一定范围内检测到病情。 计数器(58)可以耦合到设备中的其他计数器(58),用于确定高计数操作和/或某些量化器。

    STATE GROUPING FOR ELEMENT UTILIZATION
    8.
    发明申请
    STATE GROUPING FOR ELEMENT UTILIZATION 审中-公开
    元素利用的状态分组

    公开(公告)号:WO2012103151A2

    公开(公告)日:2012-08-02

    申请号:PCT/US2012/022444

    申请日:2012-01-24

    CPC classification number: G06F17/505 G06F8/447 G06F9/4498 G06F17/5054

    Abstract: Embodiments of a system and method for generating an image configured to program a parallel machine from source code are disclosed. One such parallel machine includes a plurality of state machine elements (SMEs) grouped into pairs, such that SMEs in a pair have a common output. One such method includes converting source code into an automaton comprising a plurality of interconnected states, and converting the automaton into a netlist comprising instances corresponding to states in the automaton, wherein converting includes pairing states corresponding to pairs of SMEs based on the fact that SMEs in a pair have a common output. The netlist can be converted into the image and published.

    Abstract translation: 公开了用于生成被配置为从源代码对并行机器进行编程的图像的系统和方法的实施例。 一个这样的并行机器包括分组为成对的多个状态机元件(SME),使得一对中的SME具有公共输出。 一种这样的方法包括将源代码转换为包括多个互连状态的自动机,并且将该自动机转换成包括与自动机中的状态对应的实例的网表,其中转换包括基于以下事实的转换包括与SME对相对应的配对状态 一双有共同的输出。 网表可以转换成图像并发布。

    METHOD AND APPARATUS FOR COMPILING REGULAR EXPRESSIONS
    9.
    发明申请
    METHOD AND APPARATUS FOR COMPILING REGULAR EXPRESSIONS 审中-公开
    编制规则表达的方法和装置

    公开(公告)号:WO2012103143A2

    公开(公告)日:2012-08-02

    申请号:PCT/US2012/022435

    申请日:2012-01-24

    Abstract: Apparatus, systems, and methods for a compiler are described. One such compiler converts source code into an automaton comprising states and transitions between the states, wherein the states in the automaton include a special purpose state that corresponds to a special purpose hardware element. The compiler converts the automaton into a netlist, and places and routes the netlist to provide machine code for configuring a target device.

    Abstract translation: 描述了用于编译器的装置,系统和方法。 一种这样的编译器将源代码转换成包括状态之间的自动机和状态之间的转换,其中自动机中的状态包括对应于专用硬件元件的专用状态。 编译器将自动机转换为网表,并放置和路由网表以提供用于配置目标设备的机器代码。

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