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1.发明申请
公开(公告)号：WO2022055829A1
公开(公告)日：2022-03-17
申请号：PCT/US2021/049151
申请日：2021-09-03
发明人： HULTON, David , CHRITZ, Jeremy
摘要： Examples of systems and method described herein provide for the processing of image codes (e.g., a binary embedding) at a memory system including a Hamming processing unit. Such images codes may generated by various endpoint computing devices, such as Internet of Things (IoT) computing devices, Such devices can generate a Hamming processing request, having an image code of the image, to compare that representation of the image to other images (e.g., in an image dataset) to identify a match or a set of neural network results. Advantageously, examples described herein may be used in neural networks to facilitate the processing of datasets, so as to increase the rate and amount of processing of such datasets. For example, comparisons of image codes can be performed "closer" to the memory devices, e.g., at a processing unit having memory devices.
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2.发明申请
公开(公告)号：WO2022055828A1
公开(公告)日：2022-03-17
申请号：PCT/US2021/049146
申请日：2021-09-03
发明人： HULTON, David , CHRITZ, Jeremy
摘要： Examples of systems and method described herein provide for the processing of image codes (e.g., a binary embedding) at a memory die. Such images codes may generated by various endpoint computing devices, such as Internet of Things (IoT) computing devices. Such devices can generate a Hamming processing command, having an image code of the image, to compare that representation of the image to other images (e.g., in an image dataset) to identify a match or a set of neural network results. Advantageously, examples described herein may be used in neural networks to facilitate the processing of datasets, so as to increase the rate and amount of processing of such datasets. For example, comparisons of image codes can be performed on a memory die itself, like a memory die of a NAND memory device.
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3.发明申请
公开(公告)号：WO2019014383A1
公开(公告)日：2019-01-17
申请号：PCT/US2018/041695
申请日：2018-07-11
IPC分类号： H04L12/781 , H04L12/751 , H04L12/707
摘要： Methods, systems, and devices for signal processing and wireless communication are described. For example, a device may include a plurality of antennas operable to transmit and receive communication packets via a plurality of communication protocols and an integrated circuit chip coupled to the plurality of antennas. The integrated circuit chip may comprise a first and a second plurality of processing elements. The first plurality of processing elements may be operable to receive communication packets via a first one of a plurality of communication protocols and process an optimal route. The second plurality of processing elements may be communicatively coupled to the first plurality of processing elements and operable to determine the optimal route to transmit the communication packets from a source device to a destination device based, at least in part, on transmission characteristics associated with at least one of the source or destination devices.
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公开(公告)号：WO2022119822A1
公开(公告)日：2022-06-09
申请号：PCT/US2021/061170
申请日：2021-11-30
发明人： CHRITZ, Jeremy , HULTON, David
IPC分类号： G06F21/71 , G06F21/33 , G06F21/60 , G06F12/14 , G06F12/0866 , G06F12/0875 , G06F12/1045 , G06F11/08
摘要： Examples of systems and method described herein provide for accessing memory devices and, concurrently, generating access codes using an authenticated stream cipher at a memory controller. For example, a memory controller may use a memory access request to, concurrently, perform translation logic and/or error correction on data associated with the memory access request; while also utilizing the memory address as an initialization vector for an authenticated stream cipher to generate an access code. The error correction may be performed subsequent to address translation for a write operation (or prior to address translation for a read operation) to improve processing speed of memory access requests at a memory controller; while the memory controller also generates the encrypted access code.
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5.发明申请
公开(公告)号：WO2022119819A1
公开(公告)日：2022-06-09
申请号：PCT/US2021/061165
申请日：2021-11-30
发明人： CHRITZ, Jeremy , HULTON, David
摘要： Examples of systems and method described herein or generating, in a memory controller and/or memory device, access codes for memory regions of the memory device using authentication logic, and for accessing the memory device using the access codes. For example, a memory controller and/or a coupled memory device may generate access codes that a host computing device may include in a memory access request to access one or more memory regions of the memory device. Data read or written at the memory device may in some examples only be accessed in accordance with the access codes for memory regions of the memory device. Accordingly, the systems and methods described herein may provide security for specific memory regions of a memory device because the access code are updated periodically (e.g., based on obtained reset indication) or in accordance with an updated count value from a counter.
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6.发明申请
公开(公告)号：WO2022055826A1
公开(公告)日：2022-03-17
申请号：PCT/US2021/049139
申请日：2021-09-03
发明人： HULTON, David , CHRITZ, Jeremy
摘要： Examples of systems and method described herein provide for the processing of image codes (e.g., a binary embedding) at a memory controller with various memory devices. Such images codes may generated by various endpoint computing devices, such as Internet of Things (IoT) computing devices, Such devices can generate a Hamming processing request, having an image code of the image, to compare that representation of the image to other images (e.g., in an image dataset) to identify a match or a set of neural network results. Advantageously, examples described herein may be used in neural networks to facilitate the processing of datasets, so as to increase the rate and amount of processing of such datasets. For example, comparisons of image codes can be performed "closer" to the memory devices, e.g., at the memory controller coupled to memory devices.
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7.发明申请
公开(公告)号：WO2020263583A1
公开(公告)日：2020-12-30
申请号：PCT/US2020/037246
申请日：2020-06-11
摘要： Methods, apparatuses, and systems for repairing defective memory cells in regions of a memory array associated with high or low priority levels are disclosed. A repair address generator may be configured to generate a memory address map for repair (e.g., blowing fuses at a fuse circuit), depending on whether certain applications may operate at a high priority level indicative of a low bit error rate or a low priority level indicative of a higher bit error rate. For example, a specified error rate associated with a low priority level may correspond to a threshold error rate for certain applications, such as a neural network application that stores trained weights. Such neural network applications may access trained weights being partially stored in defective memory cells, with the least significant bits of such trained weights being stored in defective memory cells that are not repaired according to the memory address map.
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