公开(公告)号：WO0175893A2

公开(公告)日：2001-10-11

申请号：PCT/US0140413

申请日：2001-03-30

Applicant: MICRON TECHNOLOGY INC

Inventor： ROOHPARVAR FRANKIE F ,  WIDMER KEVIN C

IPC: G11C16/02 ,  G11C7/10 ,  G11C16/22 ,  G11C16/26 ,  G11C

CPC classification number: G11C7/24 ,  G11C7/1072 ,  G11C16/22

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory device can comprise an array of memory cells having N addressable sectors, and control circuitry to control erase or write operations on the array of memory cells. Protection circuitry can be coupled to the control circuitry to selectively prevent erase or write operations from being performed on both first and last sectors of the N addressable sectors. The protection circuitry can comprise a multi-bit register having a first bit corresponding to the first sector and a second bit corresponding to the last sector.

Abstract translation: 同步闪速存储器包括非易失性存储器单元阵列。 存储器件具有与SDRAM兼容的封装配置。 存储器件可以包括具有N个可寻址扇区的存储器单元的阵列，以及用于控制对存储器单元阵列的擦除或写入操作的控制电路。 保护电路可以耦合到控制电路，以选择性地防止在N个可寻址扇区的第一和最后扇区上执行擦除或写入操作。 保护电路可以包括具有对应于第一扇区的第一位和与最后扇区相对应的第二位的多位寄存器。