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公开(公告)号：WO2020106502A1
公开(公告)日：2020-05-28
申请号：PCT/US2019/061052
申请日：2019-11-13
Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC
Inventor： ZARAR, Shuayb M. , AMBARDEKAR, Amol Ashok , ZHANG, Jun
Abstract: A method of performing matrix computations includes receiving a compression-encoded matrix including a plurality of rows. Each row of the compression-encoded matrix has a plurality of defined element values and, for each such defined element value, a schedule tag indicating a schedule for using the defined element value in a scheduled matrix computation. The method further includes loading the plurality of rows of the compression-encoded matrix into a corresponding plurality of work memory banks, and providing decoded input data to a matrix computation module configured for performing the scheduled matrix computation. For each work memory bank, a next defined element value and a corresponding schedule tag are read. If the schedule tag meets a scheduling condition, the next defined element value is provided to the matrix computation module. Otherwise, a default element value is provided to the matrix computation module.
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公开(公告)号：WO2018194995A1
公开(公告)日：2018-10-25
申请号：PCT/US2018/027836
申请日：2018-04-16
Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC
Inventor： MCBRIDE, Chad Balling , AMBARDEKAR, Amol Ashok , CEDOLA, Kent D. , BOBROV, Boris , PETRE, George , WALL, Larry Marvin
Abstract: An exemplary artificial intelligence/machine learning hardware computing environment having an exemplary DNN module cooperating with one or more memory components can perform data sharing and distribution as well reuse of a buffer data to reduce the number of memory component read/writes thereby enhancing overall hardware performance and reducing power consumption. Illustratively, data from a cooperating memory component is read according to a selected operation of the exemplary hardware and written to corresponding other memory component for use by one or more processing elements (e.g., neurons). The data is read in such a manner to optimize the engagement of the one or more processing elements for each processing cycle as well as to reuse data previously stored in the one or more cooperating memory components. Operatively, the written data is copied to a shadow memory buffer prior to being consumed by the processing elements.
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3.发明申请
公开(公告)号：WO2018194850A1
公开(公告)日：2018-10-25
申请号：PCT/US2018/026357
申请日：2018-04-06
Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC
Inventor： PETRE, George , MCBRIDE, Chad Balling , AMBARDEKAR, Amol Ashok , CEDOLA, Kent D. , BOBROV, Boris , WALL, Larry Marvin
IPC: G06F15/80 , G06F12/0862 , G06F9/50
Abstract: The performance of a neural network (NN) can be limited by the number of operations being performed. Using a line buffer that is directed to shift a memory block by a selected shift stride for cooperating neurons, data that is operatively residing memory and which would require multiple write cycles into a cooperating line buffer can be processed as in a single line buffer write cycle thereby enhancing the performance of a NN/DNN. A controller and/or iterator can generate one or more instructions having the memory block shifting values for communication to the line buffer. The shifting values can be calculated using various characteristics of the input data as well as the NN/DNN inclusive of the data dimensions. The line buffer can read data for processing, shift the data of the memory block and write the data in the line buffer for subsequent processing.
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公开(公告)号：WO2019125708A1
公开(公告)日：2019-06-27
申请号：PCT/US2018/062690
申请日：2018-11-28
Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC
Inventor： AMBARDEKAR, Amol Ashok , MCBRIDE, Chad Balling , PETRE, George , CEDOLA, Kent D. , WALL, Larry Marvin
CPC classification number: G06F1/3243 , G06F1/3275 , G06N3/04 , G06N3/0454 , G06N3/063
Abstract: Techniques to provide for improved (i.e., reduced) power consumption in an exemplary neural network (NN) and/or Deep Neural Network (DNN) environment using data management. Improved power consumption in the NN/DNN may be achieved by reducing a number of bit flips needed to process operands associated with one or more storages. Reducing the number bit flips associated with the NN/DNN may be achieved by multiplying an operand associated with a first storage with a plurality of individual operands associated with a plurality of kernels of the NN/DNN. The operand associated with the first storage may be neuron input data and the plurality of individual operands associated with the second storage may be weight values for multiplication with the neuron input data. The plurality of kernels may be arranged or sorted and subsequently processed in a manner that improves power consumption in the NN/DNN.
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5.发明申请
公开(公告)号：WO2018194939A1
公开(公告)日：2018-10-25
申请号：PCT/US2018/027674
申请日：2018-04-13
Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC
Inventor： MCBRIDE, Chad Balling , AMBARDEKAR, Amol Ashok , CEDOLA, Kent D. , PETRE, George , WALL, Larry Marvin , BOBROV, Boris
Abstract: A deep neural network (DNN) processor is configured to execute layer descriptors in layer descriptor lists. The descriptors define instructions for performing a forward pass of a DNN by the DNN processor. The layer descriptors can also be utilized to manage the flow of descriptors through the DNN module. For example, layer descriptors can define dependencies upon other descriptors. Descriptors defining a dependency will not execute until the descriptors upon which they are dependent have completed. Layer descriptors can also define a "fence," or barrier, function that can be used to prevent the processing of upstream layer descriptors until the processing of all downstream layer descriptors is complete. The fence bit guarantees that there are no other layer descriptors in the DNN processing pipeline before the layer descriptor that has the fence to be asserted is processed.
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Patent Agency Ranking
公开(公告)号：WO2015112653A1
公开(公告)日：2015-07-30
申请号：PCT/US2015/012331
申请日：2015-01-22
Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC
Inventor： AMBARDEKAR, Amol Ashok , HUYBREGTS, Christopher Leonard , WALL, Larry , HOUSHANGI, Damoun , PATHAK, Hrishikesh
CPC classification number: G06F17/30256 , G06F17/30144 , G06F17/30247 , G06F17/3053 , G06F17/30598 , G06F17/3079 , G06F17/3087 , G06K9/00671 , G06K9/6202 , G06K9/6227 , G06K2209/27
Abstract: A computing device having adaptable image search and methods for operating an image recognition program on the computing device are disclosed herein. An image recognition program may receive a query from a user and a target image within which a search based on the query is to be performed using one or more of a plurality of locally stored image recognition models, which are determined to be able to perform the search with sufficiently high confidence. The query may comprise text that is typed or converted from speech. The image recognition program performs the search within the target image for a target region of the target image using at least one selected image recognition model stored locally, and returns a search result to the user.
Abstract translation: 本文公开了具有适应性图像搜索的计算设备和用于在计算设备上操作图像识别程序的方法。 图像识别程序可以从用户和目标图像接收查询，在所述目标图像中，基于查询的搜索将使用多个本地存储的图像识别模型中的一个或多个来执行，所述多个本地存储的图像识别模型被确定为能够执行 搜索足够高的信心。 查询可以包括从语音输入或转换的文本。 图像识别程序使用本地存储的至少一个所选择的图像识别模型，在目标图像的目标区域内执行搜索，并将搜索结果返回给用户。
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公开(公告)号：WO2022140001A1
公开(公告)日：2022-06-30
申请号：PCT/US2021/060413
申请日：2021-11-23
Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC
Inventor： SAWHNEY, Harpreet Singh , XU, Ning , AMBARDEKAR, Amol Ashok , OLAFENWA, Moses Obadeji
Abstract: An image data annotation system automatically annotates a physical object within individual images frames of an image sequence with relevant object annotations based on a three-dimensional (3D) model of the physical object. Annotating the individual image frames with object annotations includes updating individual image frames within image input data to generate annotated image data that is suitable for reliably training a DNN object detection architecture. Exemplary object annotations that the image data annotation system can automatically apply to individual image frames include, inter alia, object pose, image pose, object masks, 3D bounding boxes composited over the physical object, 2D bounding boxes composited over the physical object, and/or depth map information. Annotating the individual image frames may be accomplished by aligning the 3D model of the physical object with a multi-view reconstruction of the physical object that is generated by inputting an image sequence into a Structure-from-Motion and/or Multi-view Stereo pipeline.
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公开(公告)号：WO2020236315A1
公开(公告)日：2020-11-26
申请号：PCT/US2020/026021
申请日：2020-03-31
Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC
Inventor： SAWHNEY, Harpreet Singh , KONIN, Andrey , GITHINJI, Bilha-Catherine W. , AMBARDEKAR, Amol Ashok , GUYMAN, William Douglas , ZIA, Muhammad Zeeshan , XU, Ning , TANG, Sheng Kai , URBINA ESCOS, Pedro
Abstract: A method for object recognition includes, at a computing device, receiving an image of a real-world object. An identity of the real-world object is recognized using an object recognition model trained on a plurality of computer-generated training images. A digital augmentation model corresponding to the real-world object is retrieved, the digital augmentation model including a set of augmentation-specific instructions. A pose of the digital augmentation model is aligned with a pose of the real-world object. An augmentation is provided, the augmentation associated with the real-world object and specified by the augmentation-specific instructions.
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9.发明申请
公开(公告)号：WO2018194993A1
公开(公告)日：2018-10-25
申请号：PCT/US2018/027834
申请日：2018-04-16
Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC
Inventor： AMBARDEKAR, Amol Ashok , CEDOLA, Kent D. , WALL, Larry Marvin , BOBROV, Boris , PETRE, George , MCBRIDE, Chad Balling
IPC: G06N3/063
Abstract: A deep neural network (DNN) processor is configured to execute descriptors in layer descriptor lists. The descriptors define instructions for performing a pass of a DNN by the DNN processor. Several types of descriptors can be utilized: memory-to-memory move (M2M) descriptors; operation descriptors; host communication descriptors; configuration descriptors; branch descriptors; and synchronization descriptors. A DMA engine uses M2M descriptors to perform multi-dimensional strided DMA operations. Operation descriptors define the type of operation to be performed by neurons in the DNN processor and the activation function to be used by the neurons. M2M descriptors are buffered separately from operation descriptors and can be executed at soon as possible, subject to explicitly set dependencies. As a result, latency can be reduced and, consequently, neurons can complete their processing faster. The DNN module can then be powered down earlier than it otherwise would have, thereby saving power.
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公开(公告)号：WO2018194845A1
公开(公告)日：2018-10-25
申请号：PCT/US2018/026352
申请日：2018-04-06
Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC
Inventor： PETRE, George , MCBRIDE, Chad Balling , AMBARDEKAR, Amol Ashok , CEDOLA, Kent D. , BOBROV, Boris , WALL, Larry Marvin
IPC: G06F13/28
Abstract: A direct memory access (DMA) engine may be responsible to enable and control DMA data flow within a computing system. The DMA engine moves blocks of data, associated with descriptors in a plurality of queues, from a source to a destination memory location or address, autonomously from control by a computer system's processor. Based on analysis of the data blocks linked to the descriptors in the queues, the DMA engine and its associated DMA fragmenter ensure that data blocks stored linked to descriptors in the queues do not remain idle for an exorbitant period of time. The DMA fragmenter may divide large data blocks into smaller data blocks to ensure that the processing of large data blocks does not preclude the timely processing of smaller data blocks associated with one or more descriptors in the queues. The data blocks stored may be two-dimensional data blocks.
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