Abstract:
The technology described herein provides a bit vector search index for a search system. The bit vector search index comprises a data structure for indexing data about terms from a corpus of documents. The data structure includes a number of bit vectors. Each bit vector comprises an array of bits and corresponds to a different set of terms. Bits in the bit vector are used to represent whether at least one document corresponding to the bit includes at least one term from the set of terms corresponding to the bit vector.
Abstract:
In some examples, computer memory content movement may include ascertaining a request associated with content of computer memory. Based on a determination that the request is directed to the content that is to be moved from a source of the computer memory to a destination of the computer memory, a determination may be made as to whether the content is at the source, is in a process of being moved from the source to the destination, or has been moved from the source to the destination. Based on a determination that the content is at the source, the request may be performed using the source. Based on a determination that the content is in the process of being moved, the request may be performed using the source. Further, based on a determination that the content has been moved, the request may be performed using the destination.
Abstract:
In some examples, performance counters for computer memory may include ascertaining a request associated with a memory address range of computer memory. The memory address range may be assigned to a specified performance tier of a plurality of specified performance tiers. A performance value associated with a performance attribute of the memory address range may be ascertained, and a weight value may be determined. Based on the ascertained request and the weight value, a count value associated with a counter associated with the memory address range may be incremented. A determination may be made as to whether the memory address range is to be assigned to a different specified performance tier of the plurality of specified performance tiers. Based on a determination that the memory address range is to be assigned to the different specified performance tier, the memory address range may be assigned to the specified different performance tier.
Abstract:
In some examples, performance counters for computer memory may include ascertaining a request associated with a memory address range of computer memory. The memory address range may be assigned to a specified performance tier of a plurality of specified performance tiers. A performance value associated with a performance attribute of the memory address range may be ascertained, and a weight value may be determined. Based on the ascertained request and the weight value, a count value associated with a counter associated with the memory address range may be incremented. A determination may be made as to whether the memory address range is to be assigned to a different specified performance tier of the plurality of specified performance tiers. Based on a determination that the memory address range is to be assigned to the different specified performance tier, the memory address range may be assigned to the specified different performance tier.
Abstract:
A compressed memory is divided into a plurality of segments, each segment is divided into a plurality of sub-segments, and each sub-segment in an uncompressed data space is compressed into block (s) in a compressed data space. Upon a read request to a sub-segment in a segment in compressed memory is received, the corresponding entry is firstly determined based on a first level address mapping between the sub-segment and the entry, and then the corresponding block (s) is determined based on a second level address mapping between the entry and the block (s). By use of two-level address mappings, the size of entry can be reduced, thereby achieving low metadata overhead. Moreover, the proposed data layout for compressed memory.
Abstract:
A key-value storage system is described herein for interacting with key-value entries in a content store using a resource-efficient index. The index provides a data structure that includes a plurality of hash buckets. Each hash bucket includes a linked list of hash bucket units. The key-value storage system stores hash entries in each linked list of hash bucket units in a distributed manner between an in-memory index store and a secondary index store, based on time of their creation. The key-value storage system is further configured to store hash entries in a particular collection of linked hash bucket units in a chronological order to reflect time of their creation. The index further includes various tunable parameters that affect the performance of the key-value storage system.