CLEAR CHANNEL ASSESSMENT
    1.
    发明申请

    公开(公告)号:WO2018104710A1

    公开(公告)日:2018-06-14

    申请号:PCT/GB2017/053643

    申请日:2017-12-04

    Abstract: A radio receiver (5) is arranged to receive radio signals. The radio receiver (5) includes a tuner (4), which outputs an electronic signal representing radio waves received by the radio receiver; a correlator (18), which cross-correlates a predetermined signal pattern with the electronic signal, and outputs a correlation signal; and a clear channel assessment module (22). The clear channel assessment module determines when the number of peaks in the correlation signal, over a fixed time window, exceeds a threshold count value, and outputs a busy signal in response to determining that the number of peaks exceeds the threshold count value.

    DEMODULATOR FOR USE IN RADIO COMMUNICATION RECEIVERS

    公开(公告)号:WO2018104716A1

    公开(公告)日:2018-06-14

    申请号:PCT/GB2017/053652

    申请日:2017-12-04

    Abstract: A radio receiver device (20) is arranged to receive a radio signal (10) modulated with a data packet including an address portion. The radio receiver comprises: a synchronisation circuit portion (28) arranged to produce synchronisation information corresponding to the data packet; a demodulation circuit portion (22) comprising a correlator (30), wherein said demodulation circuit portion is arranged to receive the radio signal 10 and to produce an estimate of the address portion (38) comprising a plurality of demodulated bits using said correlator (30) and the synchronisation information; an address checking circuit portion (26) arranged to receive the plurality of demodulated bits, to check said plurality of demodulated bits for a predetermined bit pattern, and to produce a match flag (42) if it determines that the plurality of demodulated bits corresponds to the predetermined bit pattern. The radio receiver device is arranged such that, upon detecting an upcoming timeout event, the demodulation circuit portion (22) sends a timeout warning signal to the address checking circuit portion (26) using a handshaking channel (46) therebetween; said address checking circuit portion (26) being arranged such that, if it receives the timeout warning signal, it stops checking the plurality of demodulated bits for the predetermined bit pattern.

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