公开(公告)号：WO2012097119A1

公开(公告)日：2012-07-19

申请号：PCT/US2012/021025

申请日：2012-01-12

Applicant: ORACLE INTERNATIONAL CORPORATION ,  SMITH, Alan, P. ,  MASLEID, Robert, P. ,  KONSTADINIDIS, Georgios

Inventor： SMITH, Alan, P. ,  MASLEID, Robert, P. ,  KONSTADINIDIS, Georgios

IPC: H03K3/037 ,  G06F17/50

CPC classification number: H03K3/0372 ,  G06F17/505 ,  G06F17/5068

Abstract: A method for determining flop circuit types (101, 102) includes performing a layout of an IC design (100) including arranging master and slave latches (102: M,5) of each of a plurality of flops to receive first (L-clk) and second clock (Pclk) signals, respectively. The initial IC design may then be implemented (e.g., on a silicon substrate). After implementation, the IC may be operated in first and second modes. In the first mode, the master latch of each flop (102 M) is coupled to receive a first clock signal (L-clk). In the second mode, the first clock signal (L-clk) is inhibited and the master latch (102: M) is held transparent. The slave latch of each flop (101, 102: M) operates according to a second clock signal (Pclk) in both the first and second modes. The method further includes determining, for each flop, (101, 102) whether that flop is to operate as a master-slave flip-flop (102) or as a pulse flop (101) in a subsequent revision of the IC.

Abstract translation: 一种用于确定触发器电路类型（101,102）的方法包括执行IC设计（100）的布局，包括布置多个触发器中的每一个的主和从锁存器（102：M，5）以接收第一（L-clk ）和第二时钟（Pclk）信号。 然后可以实现初始IC设计（例如，在硅衬底上）。 实施后，IC可以在第一和第二模式下操作。 在第一模式中，每个触发器（102M）的主锁存器被耦合以接收第一时钟信号（L-clk）。 在第二模式中，第一时钟信号（L-clk）被禁止，主锁存器（102：M）保持透明。 每个触发器（101,102：M）的从锁存器根据第一和第二模式中的第二时钟信号（Pclk）进行操作。 该方法还包括为每个触发器（101,102）确定该触发器是否在IC的随后修订中用作主从触发器（102）或作为脉冲触发器（101）。

公开(公告)号：WO2014121057A1

公开(公告)日：2014-08-07

申请号：PCT/US2014/014114

申请日：2014-01-31

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： MASLEID, Robert, P. ,  VAHIDSAFA, Ali

IPC: H04L7/02 ,  H04L25/05

CPC classification number: H03L7/00 ,  H04L7/005 ,  H04L7/02 ,  H04L25/05

Abstract: A rotational synchronizer for metastability resolution is disclosed. A synchronizer includes a plurality of M+1 latches each coupled to receive data through a common data input. The synchronizer further includes a multiplexer having a N inputs each coupled to receive data from an output of a corresponding one of the M+1 latches, and an output, wherein the multiplexer is configured to select one of its inputs to be coupled to the output. A control circuit is configured to cause the multiplexer to sequentially select outputs of the M+1 latches responsive to N successive clock pulses, and further configured to cause the M+1 latches to sequentially latch data received through the common data input.

Abstract translation: 公开了一种用于亚稳定性分辨率的旋转同步器。 同步器包括多个M + 1个锁存器，每个锁存器被耦合以通过公共数据输入来接收数据。 所述同步器还包括多路复用器，其具有N个输入端，每个输入端分别被耦合以从所述M + 1锁存器中对应的一个锁存器的输出端接收数据，以及输出端，其中，所述多路复用器被配置为选择其输入之一耦合到所述输出端 。 控制电路被配置为使得多路复用器响应于N个连续时钟脉冲顺序地选择M + 1个锁存器的输出，并且还被配置为使得M + 1锁存器顺序地锁存通过公共数据输入接收到的数据。