公开(公告)号：WO2022046298A1

公开(公告)日：2022-03-03

申请号：PCT/US2021/041111

申请日：2021-07-09

Applicant: QUALCOMM INCORPORATED

Inventor： ORUGANTI, Kalyan Kumar ,  GURRAM, Sreeram ,  THUMU, Venkata Balakrishna Reddy ,  KODLIPET, Pradeep Jayadev ,  SINGH, Diwakar ,  DESAI, Channappa ,  SHARMA, Sunil ,  SRIKANTH, Anne ,  GAO, Yandong

IPC: H01L27/11

Abstract: An IC includes a first memory block, a second memory block, and a first memory border cell between the first memory block and the second memory block. The first memory border cell includes a first memory core endcap to the first memory block on a first side of the cell. The first memory border cell further includes a second memory core endcap to the second memory block on a second side of the cell. The second side is opposite the first side. The first memory border cell further includes a memory gap portion between the first memory core endcap and the second memory core endcap. The memory gap portion provides a gap between the first memory core endcap and the second memory core endcap.

公开(公告)号：WO2018190959A1

公开(公告)日：2018-10-18

申请号：PCT/US2018/019714

申请日：2018-02-26

Applicant: QUALCOMM INCORPORATED

Inventor： ORUGANTI, Kalyan Kumar ,  DIGARI, Kailash ,  SRIVATSA, Sandeep Nellikatte

IPC: G06F1/32 ,  G11C14/00 ,  H03K3/356

Abstract: An integrated circuit is disclosed for data retention with data migration. In an example aspect, the integrated circuit includes a logic block, a memory block, and retention control circuitry coupled to the logic and memory blocks. The logic block includes multiple retention‑relevant storage devices to store first data and second data. The multiple retention-relevant storage devices include a first group of retention‑relevant storage devices to store the first data and a second group of retention-relevant storage devices to store the second data. The memory block maintains memory data in the memory block during a retention operational mode. The retention control circuitry causes the retention-relevant storage devices of the second group to be activated into multiple scan chains and also migrates the second data between the second group and the memory block using the multiple scan chains to accommodate transitions between the retention operational mode and a regular operational mode.