公开(公告)号：WO2016039857A1

公开(公告)日：2016-03-17

申请号：PCT/US2015/041394

申请日：2015-07-21

Applicant: QUALCOMM INCORPORATED

Inventor： COUTTS, Ryan Michael ,  WAI KIT, Siu ,  PENZES, Paul Ivan

IPC: H03K19/00

CPC classification number: H03K3/012 ,  G05B19/045 ,  H03K3/0372 ,  H03K17/223 ,  H03K19/0008

Abstract: Circuits and methods for reducing leakage are provided. In one example, a system (100) includes circuitry to reset a particular logic circuit (110a-110e, 120a-120d) to a state of reduced leakage. The state of reduced leakage would be known beforehand for the logic circuit. In this example, the logic circuit (110a-110e, 120a-120d) includes the combinational logic (120a-120d) as well as flip flops (110a-110e) that output a state to the combinational logic. Some of the flip flops are "SET" flip flops (assuming a 1 output value when a reset input is asserted) and some of the flip flops are "RESET" flip flops (assuming a 0 value when a reset input is asserted). The flip flops are chosen as inputs to the combinational logic so that the particular combination of zeros and ones output to the combinational logic puts the logic circuit in a state that is correlated with a desired level of leakage.

Abstract translation: 提供了减少泄漏的电路和方法。 在一个示例中，系统（100）包括将特定逻辑电路（110a-110e，120a-120d）复位到减少泄漏的状态的电路。 对于逻辑电路，预先知道减少泄漏的状态。 在该示例中，逻辑电路（110a-110e，120a-120d）包括组合逻辑（120a-120d）以及将状态输出到组合逻辑的触发器（110a-110e）。 一些触发器是“SET”触发器（当复位输入被置位时，假定为1个输出值），并且一些触发器是“RESET”触发器（假设复位输入被置位时为0）。 触发器被选择为组合逻辑的输入，使得零和一个输出到组合逻辑的特定组合将逻辑电路置于与期望的泄漏水平相关联的状态。