LOW POWER DESERIALIZER AND DEMULTIPLEXING METHOD
    1.
    发明申请
    LOW POWER DESERIALIZER AND DEMULTIPLEXING METHOD 审中-公开
    低功耗解决方案和解复用方法

    公开(公告)号:WO2009158541A1

    公开(公告)日:2009-12-30

    申请号:PCT/US2009/048720

    申请日:2009-06-25

    CPC classification number: H04Q11/04 H03M9/00

    Abstract: A deserializer circuit and method convert a serial bit stream into a parallel bit stream according to a parallel grouping. The deserializer and method include alternatingly demultiplexing a serial data stream into first and second bit streams. The first and second bit streams are respectively serially shifted along a first plurality of shift registers and a second plurality of shift registers. A first portion of the first bit stream in the first plurality of shift registers is selected and a second portion of the second bit stream in the second plurality of shift registers is also selected. A parallel group of data in a parallel data stream is formed from the first and second portions.

    Abstract translation: 解串器电路和方法根据并行分组将串行比特流转换成并行比特流。 解串器和方法包括将串行数据流交替解复用为第一和第二位流。 第一和第二比特流分别沿着第一多个移位寄存器和第二多个移位寄存器串行移位。 选择第一多个移位寄存器中的第一比特流的第一部分,并且还选择第二多个移位寄存器中的第二比特流的第二部分。 并行数据流中的并行数据组由第一和第二部分形成。

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