LOAD-REDUCED DRAM STACK
    1.
    发明申请

    公开(公告)号:WO2021178208A1

    公开(公告)日:2021-09-10

    申请号:PCT/US2021/019642

    申请日:2021-02-25

    Applicant: RAMBUS INC.

    Abstract: Power consumption in a three-dimensional stack of integrated-circuit memory dies is reduced through selective enabling/disabling of physical signaling interfaces in those dies in response to early transmission of chip identifier information relative to command execution.

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