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公开(公告)号：WO2018071107A1
公开(公告)日：2018-04-19
申请号：PCT/US2017/049755
申请日：2017-08-31
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： YUH, Jong Hak , CERNEA, Raul Adrian , LEE, Seungpil , LI, Yen-Lung , NGUYEN, Qui , TSENG, Tai-Yuan , HSU, Cynthia
Abstract: Apparatuses, systems, and methods are disclosed for accessing non-volatile memory 122. A bit line 302 is coupled to storage cells for a non-volatile memory element 123. A sense amplifier 306 is coupled to a bit line 302. A sense amplifier 306 includes a sense circuit 402 and a bias circuit 404. A sense circuit 402 senses an electrical property of a bit line 302 for reading data from one or more storage cells, and a bias circuit 404 applies a bias voltage to the bit line 302 for writing data to one or more storage cells. A bias circuit 404 and a sense circuit 402 comprise separate parallel electrical paths within a sense amplifier 306.
Abstract translation: 公开了用于访问非易失性存储器122的设备，系统和方法。位线302耦合到用于非易失性存储器元件123的存储单元。读出放大器306耦合到 位线302.感测放大器306包括感测电路402和偏置电路404.感测电路402感测用于从一个或多个存储单元读取数据的位线302的电特性，并且偏置电路404施加偏置 电压施加到位线302以将数据写入到一个或多个存储单元。 偏置电路404和读出电路402包括读出放大器306内的分开的并行电路径。
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公开(公告)号：WO2019236151A1
公开(公告)日：2019-12-12
申请号：PCT/US2019/017075
申请日：2019-02-07
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： LIN, Lei , LI, Zhoujie , CHIN, Henry , HSU, Cynthia
Abstract: An apparatus is provided that includes a plurality of memory cells, a programming circuit configured to apply a plurality of programming pulses to the memory cells, and a scanning circuit configured to repeatedly switch between performing an n-state bitscan after each programming pulse until first predetermined criteria are satisfied, and performing an m-state bitscan after each programming pulse until second predetermined criteria are satisfied, where m > n, and n > 0.
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3.发明申请
公开(公告)号：WO2019022810A1
公开(公告)日：2019-01-31
申请号：PCT/US2018/032439
申请日：2018-05-11
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： LU, Ching-Huang , KHANDELWAL, Anubhav , CHEN, Changyuan , HSU, Cynthia , DONG, Yingda
Abstract: Non-volatile storage systems and method of operating non-volatile storage systems are disclosed. A crept up voltage on a memory cell control gate adjacent to a select gate is prevented, reduced, and/or discharged. In some aspects, the crept up voltage is not allowed to happen on the memory cell next to the select gate after a sensing operation. In some aspects, the voltage may creep up on the memory cell control gate after a sensing operation, but it is discharged. Reducing and/or preventing the crept up voltage may reduce the electric field between the dummy memory cell and select gate transistor. This may prevent, or at least reduce, changes in threshold voltage of the select gate transistor. Additional problems may also be solved by a reduction of the crept up voltage on the dummy memory cell control gates.
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