公开(公告)号：WO1993026127A1

公开(公告)日：1993-12-23

申请号：PCT/US1993005504

申请日：1993-06-09

Applicant: SCIENTIFIC-ATLANTA, INC.

Inventor： SCIENTIFIC-ATLANTA, INC. ,  ROBERTSON, Neil, Charles ,  SCHUTTE, Mark, E.

IPC: H04N07/167

CPC classification number: H04K3/825 ,  H04K3/41 ,  H04K3/42 ,  H04K3/43 ,  H04K2203/14 ,  H04N7/166

Abstract: Each subscriber module circuit comprises a plurality of latches (322) each of which is associated with one of a plurality of digital to analog converters (324). Each of the digital to analog converters (324) drives one or more frequency agile oscillators (326) with its analog output to generate the jamming signals. The subscriber module is based on a sequential state machine which loads frequency control words corresponding to the jammed channels from a frequency control memory (320) into each latch (322) on a cyclic basis. In this manner, the jamming signals generated by each latch (322), digital to analog converter (324), and oscillator (326) combination can be varied easily and quickly by a memory to memory transfer and be sustained between frequency hops without any change in frequency. The circuitry lends itself easily to large scale integration and miniaturization while eliminating the need to refresh the circuit to prevent frequency change because of voltage drop.

Abstract translation: 每个用户模块电路包括多个锁存器（322），每个锁存器与多个数模转换器之一相关联。 每个数模转换器（324）用其模拟输出驱动一个或多个频率捷变振荡器（326）以产生干扰信号。 订户模块基于顺序状态机，其将循环的来自频率控制存储器（320）的对应于卡塞通道的频率控制字加载到每个锁存器（322）中。 以这种方式，每个锁存器（322），数模转换器（324）和振荡器（326）组合产生的干扰信号可以通过存储器容易且快速地改变到存储器传输，并且可以在跳频之间维持而无任何改变 频率。 该电路很容易实现大规模集成和小型化，同时不需要刷新电路以防止由于电压降而引起的频率变化。