Abstract:
An integrated circuit package (34, 34', 34'') may be implemented by stacked first, second, and third integrated circuit dies (40, 50, 60). The first and second dies (40, 50) may be bonded to each other using corresponding inter-die connection structures (74-1, 84-1) at respective interfacial surfaces facing the other die. The second die (50) may also include a metal layer (84-2) for connecting to the third die (60) at its interfacial surface with the first die (40). The metal layer (84-2) may be connected to a corresponding inter-die connection structure (64) on the side of the third die (60) facing the second die (50) through a conductive through-substrate via (84-2) and an additional metal layer (102) in a redistribution layer (96) between the second and third dies (50, 60). The third die (60) may have a different lateral outline than the second die (50).
Abstract:
An imaging system (100) may include an image sensor die (102) stacked on top of a digital signal processor (DSP) die (104). Through-oxide vias (TOVs) (128) may be formed in the image sensor die (102) and may extend at least partially into in the DSP die (104) to facilitate communications between the image sensor die (102) and the DSP die (104). The image sensor die (102) may include light shielding structures (126) for preventing reference photodiodes (116') in the image sensor die (102) from receiving light and in-pixel grid structures (200) for preventing cross-talk between adjacent pixels (116). The light shielding structure (126) may receive a desired biasing voltage through a corresponding TOV (128), an integral plug structure (190), and/or a connection that makes contact directly with a polysilicon gate (192). The in-pixel grid (200) may have a peripheral contact (200') that receives the desired biasing voltage through a light shield (210), a conductive strap (210), a TOV (300), and/or an aluminum pad (450).