公开(公告)号：WO2016141777A2

公开(公告)日：2016-09-15

申请号：PCT/CN2016/070839

申请日：2016-01-13

Applicant: SHANGHAI JING PENG INVEST MANAGEMENT CO., LTD.

Inventor： GU, Jing ,  SHIH, Po-Yi

CPC classification number: G09G3/3233 ,  G09G3/3266 ,  G09G3/3291 ,  G09G2300/0443 ,  G09G2300/0814 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2310/0262 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/0233 ,  G09G2330/028

Abstract: A pixel circuit includes a capacitor, a light emitting control transistors, a driving transistor, and multiple light emitting transistors. The light emitting control transistor includes a gate electrode coupled to a light emitting control signal, a source electrode coupled to a supply voltage, and a drain electrode. The driving transistor includes a gate electrode coupled to the capacitor, a source electrode coupled to the drain electrode of the light emitting control transistor, and a drain electrode. Each light emitting transistor includes a gate electrode coupled to a respective light emitting signal, a source electrode coupled to the drain electrode of the driving transistor, and a drain electrode coupled to a respective light emitting element. Each light emitting signal turns on the respective light emitting transistor during a respective light emitting period within a frame period to cause the respective light emitting element to emit a light. The light emitting control signal turns on the light emitting control transistor during each light emitting period within the frame period.

Abstract translation: 像素电路包括电容器，发光控制晶体管，驱动晶体管和多个发光晶体管。 发光控制晶体管包括耦合到发光控制信号的栅电极，耦合到电源电压的源电极和漏电极。 驱动晶体管包括耦合到电容器的栅电极，耦合到发光控制晶体管的漏电极的源电极和漏电极。 每个发光晶体管包括耦合到相应的发光信号的栅电极，耦合到驱动晶体管的漏电极的源电极和耦合到相应的发光元件的漏电极。 每个发光信号在帧周期内的各个发光周期期间导通相应的发光晶体管，以使各个发光元件发光。 发光控制信号在帧周期内的每个发光时段期间导通发光控制晶体管。

公开(公告)号：WO2017121166A1

公开(公告)日：2017-07-20

申请号：PCT/CN2016/103315

申请日：2016-10-25

Applicant: SHANGHAI JING PENG INVEST MANAGEMENT CO., LTD.

Inventor： GU, Jing ,  SHIH, Po-Yi

IPC: G09G3/36

CPC classification number: G09G3/3233 ,  G09G3/3266 ,  G09G3/3291 ,  G09G2300/0443 ,  G09G2300/0814 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2310/0262 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/0233 ,  G09G2330/028

Abstract: An apparatus includes a graphics pipeline and a pixel data reordering module. The graphics pipeline is configured to generate a plurality pieces of pixel data of a frame. The plurality pieces of pixel data of the frame are associated with a first order in which the plurality pieces of pixel data of the frame are to be provided to a display panel having an array of pixels. Each piece of pixel data of the frame corresponds to one pixel of the array of pixels. The array of pixels are divided into a plurality of groups of pixels. The pixel data reordering module is configured to cause the plurality pieces of pixel data of the frame to be obtained by the display panel in a second order. The second order is determined based on at least a manner in which the array of pixels are divided into the groups of pixels.

Abstract translation: 一种装置包括图形管线和像素数据重新排序模块。 图形流水线被配置为生成帧的多个像素数据。 该帧的多个像素数据与帧的多个像素数据将被提供给具有像素阵列的显示面板的第一顺序相关联。 帧的每个像素数据片段对应于像素阵列的一个像素。 像素阵列被分成多个像素组。 像素数据重新排序模块被配置为使得帧的多个像素数据以第二顺序由显示面板获得。 第二级至少基于像素阵列被分成像素组的方式来确定。