公开(公告)号：WO2015084493A2

公开(公告)日：2015-06-11

申请号：PCT/US2014/060878

申请日：2014-10-16

Applicant: THE REGENTS OF THE UNIVERSITY OF MICHIGAN

Inventor： PUSDESRIS, Joseph, Michael ,  KANG, Yiping ,  PELLEGRINI, Andrea ,  MUDGE, Trevor, Nigel ,  VANDERSLOOT, Benjamin, Allen

IPC: G06F9/30

CPC classification number: G06F12/023 ,  G06F9/30043 ,  G06F9/3826 ,  G06F9/384

Abstract: A data processing apparatus has a memory rename table for storing memory rename entries each identifying a mapping between a memory address of a location in memory and a mapped register of a plurality of registers. The mapped register is identified by a register number. In response to a store instruction, the store target memory address of the store instruction is mapped to a store destination register and so the data value is stored to the store destination register instead of memory. A memory rename entry is provided in the table to identify the mapping between the store target memory address and store destination target register. In response to a load instruction, if there is a hit in the memory rename table for the load target memory address then the loaded value can be read from the mapped register instead of memory.

Abstract translation: 数据处理装置具有存储器重命名表，用于存储每个识别存储器中的位置的存储器地址和多个寄存器的映射寄存器之间的映射的存储器重命名条目。 映射的寄存器由寄存器编号标识。 响应于存储指令，存储指令的存储目标存储器地址被映射到存储目的地寄存器，因此将数据值存储到存储目的地寄存器而不是存储器。 在表中提供存储器重命名条目以识别存储目标存储器地址和存储目的地目标寄存器之间的映射。 响应于加载指令，如果存储器重命名表中存在针对加载目标存储器地址的命中，则可以从映射的寄存器而不是存储器读取加载的值。

公开(公告)号：WO2009067219A8

公开(公告)日：2009-05-28

申请号：PCT/US2008/012935

申请日：2008-11-20

Applicant: ARM LIMITED ,  THE REGENTS OF THE UNIVERSITY OF MICHIGAN ,  BLAKE, Geoffrey ,  MUDGE, Trevor, Nigel ,  BILES, Stuart, David ,  CHONG, Nathan, Yong Seng ,  OZER, Emre ,  DRESLINSKI, Ronald, George

Inventor： BLAKE, Geoffrey ,  MUDGE, Trevor, Nigel ,  BILES, Stuart, David ,  CHONG, Nathan, Yong Seng ,  OZER, Emre ,  DRESLINSKI, Ronald, George

IPC: G06F9/46

Abstract: A hardware transactional memory 12, 14, 16, 18, 20 is provided within a multiprocessor 4, 6, 8, 10 system with coherency control and hardware transaction memory control circuitry 22 that serves to at least partially manage the scheduling of processing transactions in dependence upon conflict data 26, 28, 30. The conflict data characterises previously encountered conflicts between processing transactions. The scheduling is performed such that a candidate processing transaction will not be scheduled if the conflict data indicates that one of the already running processing transactions has previously conflicted with the candidate processing transaction.