公开(公告)号：WO2015066629A1

公开(公告)日：2015-05-07

申请号：PCT/US2014/063723

申请日：2014-11-03

Applicant: THE TRUSTEES OF COLUMBIA UNIVERSITY IN THE CITY OF NEW YORK

Inventor： SEOK, Mingoo ,  KINGET, Peter, R. ,  YANG, Teng ,  KIM, Seongjong

IPC: G05F3/24 ,  G05F3/20 ,  G05F3/16

CPC classification number: G01K7/01 ,  G05F3/245

Abstract: Circuits for temperature monitoring are provided having a first voltage output and a second voltage output comprising: a first transistor having a first transistor input, a first transistor output, and a first transistor control, wherein the first transistor input is connected to a supply voltage; a first diode having a first diode input and a first diode output, wherein the first diode output is connected to ground and the first diode input is connected to the first transistor output, the first transistor control and the first voltage output; a second transistor having a second transistor input, a second transistor output, and a second transistor control, wherein the second transistor input is connected to a supply voltage; a second diode having a second diode input and a second diode output, wherein the second diode input is connected to the second transistor output, the second transistor control, and the second voltage output.

Abstract translation: 提供了具有第一电压输出和第二电压输出的用于温度监测的电路，包括：具有第一晶体管输入，第一晶体管输出和第一晶体管控制的第一晶体管，其中所述第一晶体管输入连接到电源电压; 第一二极管，其具有第一二极管输入和第一二极管输出，其中所述第一二极管输出连接到地，所述第一二极管输入连接到所述第一晶体管输出，所述第一晶体管控制和所述第一电压输出; 具有第二晶体管输入，第二晶体管输出和第二晶体管控制的第二晶体管，其中所述第二晶体管输入连接到电源电压; 具有第二二极管输入和第二二极管输出的第二二极管，其中所述第二二极管输入连接到所述第二晶体管输出，所述第二晶体管控制和所述第二电压输出。

公开(公告)号：WO2020139895A1

公开(公告)日：2020-07-02

申请号：PCT/US2019/068495

申请日：2019-12-24

Applicant: THE TRUSTEES OF COLUMBIA UNIVERSITY IN THE CITY OF NEW YORK

Inventor： SEOK, Mingoo ,  JIANG, Zhewei ,  SEO, Jae-sun ,  YIN, Shihui

IPC: G11C14/00

Abstract: In some embodiments, an in-memory-computing SRAM macro based on capacitive- coupling computing (C3) (which is referred to herein as "C3SRAM") is provided. In some embodiments, a C3SRAM macro can support array-level fully parallel computation, multi-bit outputs, and configurable multi-bit inputs. The macro can include circuits embedded in bitcells and peripherals to perform hardware acceleration for neural networks with binarized weights and activations in some embodiments. In some embodiments, the macro utilizes analog-mixed- signal capacitive-coupling computing to evaluate the main computations of binary neural networks, binary-multiply-and-accumulate operations. Without needing to access the stored weights by individual row, the macro can assert all of its rows simultaneously and form an analog voltage at the read bitline node through capacitive voltage division, in some embodiments. With one analog-to-digital converter (ADC) per column, the macro cab realize fully parallel vector-matrix multiplication in a single cycle in accordance with some embodiments.