公开(公告)号：WO2009102948A3

公开(公告)日：2009-10-08

申请号：PCT/US2009034044

申请日：2009-02-13

Applicant: UNIV ARIZONA STATE ,  LESHNER SAMUEL ,  VRUDHULA SARMA

Inventor： LESHNER SAMUEL ,  VRUDHULA SARMA

IPC: H03K19/08 ,  G06F7/02 ,  G06N3/063

CPC classification number: H03K19/0813

Abstract: Embodiments of a threshold logic element are provided. Preferably, embodiments of the threshold logic element discussed herein have low leakage power and high performance characteristics. In the preferred embodiment, the threshold logic element is a threshold logic latch (TLL). The TLL is a dynamically operated current-mode threshold logic cell that provides fast and efficient implementation of digital logic functions. The TLL can be operated synchronously or asynchronously and is fully compatible with standard Complementary Metal-Oxide-Semiconductor (CMOS) technology.

Abstract translation: 提供阈值逻辑元件的实施例。 优选地，本文讨论的阈值逻辑元件的实施例具有低泄漏功率和高性能特性。 在优选实施例中，阈值逻辑元件是阈值逻辑锁存器（TLL）。 TLL是一种动态操作的电流模式阈值逻辑单元，可快速有效地实现数字逻辑功能。 TLL可以同步或异步操作，并与标准互补金属氧化物半导体（CMOS）技术完全兼容。