公开(公告)号：WO1996007986A2

公开(公告)日：1996-03-14

申请号：PCT/US1995011338

申请日：1995-09-06

Applicant: UNIVERSITY OF SOUTH FLORIDA

Inventor： UNIVERSITY OF SOUTH FLORIDA ,  KOVAC¿, Mario ,  RANGANATHAN, Nagarajan

IPC: G06T00/00

CPC classification number: G06T9/007

Abstract: A fully pipelined VLSI circuit structure for implementing the JPEG baseline image compression standard. The circuit structure exploits the principles of pipelining and parallelism to the maximum extent in order to obtain high speed and throughput. The entire structure is designed to be implemented on a single VLSI chip to yield a clock rate of about 100 MHz which would allow an input rate of 30 frames per second for 1024 x 1024 color images.

Abstract translation: 完全流水线的VLSI电路结构，用于实现JPEG基线图像压缩标准。 电路结构在最大程度上利用流水线和并行的原理，以获得高速度和吞吐量。 整个结构被设计为在单个VLSI芯片上实现，以产生约100MHz的时钟速率，这将允许1024×1024彩色图像的每秒30帧的输入速率。

公开(公告)号：WO2005057628A2

公开(公告)日：2005-06-23

申请号：PCT/US2004/040989

申请日：2004-12-08

Applicant: UNIVERSITY OF SOUTH FLORIDA ,  RANGANATHAN, Nagarajan ,  HANCHATE, Narender

Inventor： RANGANATHAN, Nagarajan ,  HANCHATE, Narender

IPC: H01L

CPC classification number: H03K19/00361 ,  H03K17/162 ,  H03K17/6872 ,  H03K19/0013 ,  H03K2217/0036

Abstract: An efficient design methodology in accordance with the present invention is described for reducing the leakage power in CMOS circuits. The method and apparatus in accordance with the present invention yields better leakage reduction as the threshold voltage decreases and hence aids in further reduction of supply voltage and minimization of transistor sizes. Unlike other leakage control techniques, the technique of the present invention does not need any control circuitry to monitor the states of the circuit. Hence, avoiding the sacrifice of obtained leakage power reduction in the form of dynamic power consumed by the additional circuitry to control the overall circuit states.

Abstract translation: 描述了根据本发明的有效设计方法，用于减少CMOS电路中的泄漏功率。 根据本发明的方法和装置随着阈值电压的降低而产生更好的泄漏减少，从而有助于进一步降低电源电压并最小化晶体管尺寸。 与其他泄漏控制技术不同，本发明的技术不需要任何控制电路来监测电路的状态。 因此，避免以附加电路消耗的动态功率的形式牺牲获得的泄漏功率降低以控制总体电路状态。

公开(公告)号：WO2017210005A1

公开(公告)日：2017-12-07

申请号：PCT/US2017/033769

申请日：2017-05-22

Applicant: UNIVERSITY OF SOUTH FLORIDA

Inventor： ADITHAM, Santosh, Kumar ,  RANGANATHAN, Nagarajan

IPC: G06F12/14 ,  G06F21/52 ,  G06F21/56 ,  H04L9/18 ,  H04L29/06 ,  H04N7/167

CPC classification number: H04L63/1416 ,  G06F16/9014 ,  G06F16/9024 ,  G06F21/52 ,  G06F21/554 ,  G06F21/56 ,  G06F21/566 ,  H04L9/3239 ,  H04L9/3247 ,  H04L63/0442 ,  H04L63/1441

Abstract: Various examples of methods and systems are provided for an attack detection system that can detect attacks in big data systems. The attack detection system can include security modules coupled to data nodes of the big data system. The attack detection system can identify a process executing on the respective data node. A process signature can be generated for the process executing on the data node. A determination of whether a big data system is being attacked can be based at least in part on a comparison of the process signature with at least one other process signature for the same process executing on another security module. The other process signatures are received via secure communication from the other security module.

Abstract translation: 为可以检测大数据系统中的攻击的攻击检测系统提供了各种方法和系统的示例。 攻击检测系统可以包括耦合到大数据系统的数据节点的安全模块。 攻击检测系统可以识别在相应数据节点上执行的进程。 可以为在数据节点上执行的进程生成进程签名。 至少部分地基于过程签名与在另一安全模块上执行的相同过程的至少一个其他过程签名的比较来确定大数据系统是否受到攻击。 其他进程签名通过来自其他安全模块的安全通信接收。