公开(公告)号：WO2002080368A1

公开(公告)日：2002-10-10

申请号：PCT/US2002/005176

申请日：2002-02-20

Applicant: XILINX, INC.

Inventor： KAVIANI, Alireza, S.

IPC: H03K19/00

CPC classification number: H03K19/17784 ,  H03K19/0016

Abstract: A technique for reducing leakage current in static CMOS devices by adding additional transistors in series between selected inverters and ground or power. NMOS and PMOS transistors are added to selected buffers comprised of two inverters in series. The PMOS transistor (124) is connected between the first inverter (112,114) and power (Vdd) and the NMOS transistor (126) is connected between the second inverter (128) and ground. The added transistors are controlled by a memory cell (130) to be on when the buffer is being used and off when the buffer is unused. Alternatively, no PMOS transistor is added and an existing PMOS transistor of the first inverter is manufactured to sit in a Vgg well. The same tech niques are employed with selected buffer pairs.

Abstract translation: 一种减少静态CMOS器件泄漏电流的技术，通过在所选择的逆变器之间增加额外的晶体管和接地或电源。 NMOS和PMOS晶体管被添加到由串联的两个反相器组成的选择的缓冲器中。 PMOS晶体管（124）连接在第一反相器（112,114）和功率（Vdd）之间，NMOS晶体管（126）连接在第二反相器（128）和地之间。 所添加的晶体管由存储单元（130）控制，当缓冲器被使用时，该存储器单元（130）将导通，当缓冲器未被使用时，关闭。 或者，不添加PMOS晶体管，并且制造第一反相器的现有PMOS晶体管以坐在Vgg中。 所选择的缓冲区对采用相同的技术。

公开(公告)号：WO2017136289A3

公开(公告)日：2017-08-10

申请号：PCT/US2017/015665

申请日：2017-01-30

Applicant: XILINX, INC.

Inventor： KAVIANI, Alireza, S. ,  MAIDEE, Pngstorn ,  BOLSENS, Ivo ,  DELLINGER, Eric, F.

IPC: H03K19/00

Abstract: An example integrated circuit (IC) system includes a package substrate (202) having a programmable integrated circuit (IC) (101 A) and a companion IC (103A) mounted thereon, the programmable IC including a programmable fabric (404) and the companion IC including application circuitry (107A). The IC system further includes a system-in-package (SiP) bridge (144) including a first SiP IO circuit (140A) disposed in the programmable IC, a second SiP IO circuit (142) disposed in the companion IC, and conductive interconnect (138) on the package substrate electrically coupling the first SiP IO circuit and the second SiP IO circuit. The IC System further includes first aggregation and first dispersal circuits (110, 112) in the programmable IC coupled between the programmable fabric and the first SiP IO circuit. The IC system further includes second aggregation and second dispersal circuits (126, 128) in the companion IC coupled between the application circuitry and the second SiP IO circuit.

公开(公告)号：WO2017095627A1

公开(公告)日：2017-06-08

申请号：PCT/US2016/062095

申请日：2016-11-15

Applicant: XILINX, INC.

Inventor： GANUSOV, Ilya, K. ,  FRAISSE, Henri ,  SIRASAO, Ashish ,  KAVIANI, Alireza, S.

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5054

Abstract: Disclosed approaches for processing a circuit design include identifying (604) duplicate instances (104, 106) of modules in a representation of the circuit design. A processor circuit (702) performs folding operations (610) for at least one pair of the duplicate instances of a module. One instance of the duplicates is removed (612) from the circuit design, and a multiplexer (210) is inserted (614). The multiplexer receives and selects one of the input signals to the duplicate instances and provides the selected input signal to the remaining instance. For each flip-flop (1 16) in the remaining instance, a pipelined flip-flop (204) is inserted (616, 618). Connections to a first clock signal in the remaining instance are replaced (624) with connections to a second clock signal having twice the frequency of the first clock signal. An alignment circuit (216) is inserted (626) to receive the output signal from the first instance and provide concurrent first and second output signals.

Abstract translation: 所公开的用于处理电路设计的方法包括在电路设计的表示中识别（604）模块的重复实例（104,106）。 处理器电路（702）为模块的至少一对重复实例执行折叠操作（610）。 从电路设计中删除（612）重复的一个实例，并插入多路复用器（210）（614）。 多路复用器接收并选择输入信号中的一个到复制实例，并将选择的输入信号提供给其余实例。 对于其余实例中的每个触发器（116），插入流水线触发器（204）（616,618）。 连接到其余实例中的第一时钟信号的连接被替换（624），连接到具有第一时钟信号的两倍频率的第二时钟信号。 一个对准电路（216）被插入（626）以接收来自第一实例的输出信号并提供并发的第一和第二输出信号。

公开(公告)号：WO2017136289A8

公开(公告)日：2017-08-10

申请号：PCT/US2017/015665

申请日：2017-01-30

Applicant: XILINX, INC.

Inventor： KAVIANI, Alireza, S. ,  MAIDEE, Pongstorn ,  BOLSENS, Ivo ,  DELLINGER, Eric, F.

IPC: H03K19/00

Abstract: An example integrated circuit (IC) system includes a package substrate (202) having a programmable integrated circuit (IC) (101 A) and a companion IC (103A) mounted thereon, the programmable IC including a programmable fabric (404) and the companion IC including application circuitry (107A). The IC system further includes a system-in-package (SiP) bridge (144) including a first SiP IO circuit (140A) disposed in the programmable IC, a second SiP IO circuit (142) disposed in the companion IC, and conductive interconnect (138) on the package substrate electrically coupling the first SiP IO circuit and the second SiP IO circuit. The IC System further includes first aggregation and first dispersal circuits (110, 112) in the programmable IC coupled between the programmable fabric and the first SiP IO circuit. The IC system further includes second aggregation and second dispersal circuits (126, 128) in the companion IC coupled between the application circuitry and the second SiP IO circuit.

公开(公告)号：WO2017136289A2

公开(公告)日：2017-08-10

申请号：PCT/US2017/015665

申请日：2017-01-30

Applicant: XILINX, INC.

Inventor： KAVIANI, Alireza, S. ,  MAIDEE, Pngstorn ,  BOLSENS, Ivo ,  DELLINGER, Eric, F.

IPC: H03K19/00

CPC classification number: H03K19/17744 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/15192 ,  H01L2924/15311

Abstract: An example integrated circuit (IC) system includes a package substrate (202) having a programmable integrated circuit (IC) (101 A) and a companion IC (103A) mounted thereon, the programmable IC including a programmable fabric (404) and the companion IC including application circuitry (107A). The IC system further includes a system-in-package (SiP) bridge (144) including a first SiP IO circuit (140A) disposed in the programmable IC, a second SiP IO circuit (142) disposed in the companion IC, and conductive interconnect (138) on the package substrate electrically coupling the first SiP IO circuit and the second SiP IO circuit. The IC System further includes first aggregation and first dispersal circuits (110, 112) in the programmable IC coupled between the programmable fabric and the first SiP IO circuit. The IC system further includes second aggregation and second dispersal circuits (126, 128) in the companion IC coupled between the application circuitry and the second SiP IO circuit.

Abstract translation: 示例集成电路（IC）系统包括其上安装有可编程集成电路（IC）（101A）和配套IC（103A）的封装衬底（202），所述可编程IC包括 可编程结构（404）以及包括应用电路（107A）的伴随IC。 IC系统还包括系统级封装（SiP）桥（144），其包括设置在可编程IC中的第一SiP IO电路（140A），设置在配套IC中的第二SiP IO电路（142）以及导电互连 （138），所述封装衬底电耦合所述第一SiP IO电路和所述第二SiP IO电路。 IC系统还包括耦合在可编程结构与第一SiP IO电路之间的可编程IC中的第一聚集电路和第一分散电路（110,112）。 IC系统还包括耦合在应用电路和第二SiP IO电路之间的配套IC中的第二聚合和第二分散电路（126,128）。